From patchwork Tue Sep 12 13:00:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 112305 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5156130qgf; Tue, 12 Sep 2017 06:01:42 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5pAJzNFfLfx1wbyQxGZKicITWnbTgOQ8lhpslHSkBYu3bagzi1BR/5pIpZMhG+uznmeK1U X-Received: by 10.159.207.132 with SMTP id z4mr16903390plo.95.1505221302728; Tue, 12 Sep 2017 06:01:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505221302; cv=none; d=google.com; s=arc-20160816; b=AMoFwZeP4nJXC5Cr121tjvGkWTdYW61B4k7Snus3rIgyUmvzNskLUgBgIqEq5na2Hu XFD1Ybp5+LtE4WFl5opfqup8NUKokBAYVTHBWNtBDWt8NCkeKy4H+jCvYNsf2cKGk/m4 B9GSsHcRXsUxAgTknCrJ6tMYb/7EGhu/f88SOpZIK55dlKysUUEAZAnLlTRLorTgttei BWXgmetfp7AQBxUPwr1zcb0tWzKhRrSKJnJjXR0rQf52i9xw2Rl4KowvMipNoxZFmUBh vHjVwsbSZoARxSbTevkVCIRqJ8fzrrz3vGyia0FIrrgN1+UU1ceDvpFHUO39CswSP+WU YMeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=YlaXM3KzodSC1DETM7futMB2tnEsAh2QF3RN/PP6mc8=; b=WcjhfKxddZpUfwWw/t2+/1mUhsmhWtiTRKCt5zozM3FvkIhsn8tDWN8kn9gMbu5gVk lKuw8DXHgJTtJie8x/I2dY1FLrdzfYQff8SRngxv40FdCSSxR54ZV2brihA2YRgnpHP3 T68nRQA7fzFFBBmpgcPylFEUv++aIF6u5rToKyMyuUKKz8sO6/DSlYRVIObyZ+/wtjB0 tjy34cWPoOhzOB2xqjITrUrJhotNOWU5cxWPka2lll5zid79lZyz/WeFRbKXa0uT5o0z 9K4fqvo3K+ZhJ75dGeehw1/ODG0rvXrW1T1S/VTnRoH4JJM1WAoEBMsp1wbPg5aK4UCH JzFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y2si9387522pll.163.2017.09.12.06.01.42; Tue, 12 Sep 2017 06:01:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751525AbdILNBk (ORCPT + 26 others); Tue, 12 Sep 2017 09:01:40 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6457 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751289AbdILNBh (ORCPT ); Tue, 12 Sep 2017 09:01:37 -0400 Received: from 172.30.72.58 (EHLO DGGEMS412-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHB84762; Tue, 12 Sep 2017 21:01:31 +0800 (CST) Received: from localhost (10.177.23.164) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.301.0; Tue, 12 Sep 2017 21:01:23 +0800 From: Zhen Lei To: Will Deacon , Joerg Roedel , linux-arm-kernel , iommu , Robin Murphy , linux-kernel CC: Hanjun Guo , Libin , "Zhen Lei" , Jinyue Li , "Kefeng Wang" Subject: [PATCH v2 0/3] arm-smmu: performance optimization Date: Tue, 12 Sep 2017 21:00:35 +0800 Message-ID: <1505221238-9428-1-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.0 MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.59B7DAAC.00EE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d367de313be78997ecc11c16777dbe61 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org v1 -> v2: base on (add02cfdc9bc2 "iommu: Introduce Interface for IOMMU TLB Flushing") Zhen Lei (3): iommu/arm-smmu-v3: put off the execution of TLBI* to reduce lock confliction iommu/arm-smmu-v3: add support for unmap an iova range with only one tlb sync iommu/arm-smmu: add support for unmap a memory range with only one tlb sync drivers/iommu/arm-smmu-v3.c | 52 ++++++++++++++++++++++++++++++++++---- drivers/iommu/arm-smmu.c | 10 ++++++++ drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++-------- drivers/iommu/io-pgtable-arm.c | 30 ++++++++++++++-------- drivers/iommu/io-pgtable.h | 1 + 5 files changed, 99 insertions(+), 26 deletions(-) -- 2.5.0 Tested-by: Nate Watterson