From patchwork Thu Mar 21 09:59:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 160757 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp595545jan; Thu, 21 Mar 2019 03:00:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxQgGGih3TIdsdTT496qhO+Ri+/sZcZDOhPY9Cjwce8NOIjQOmEhH39BuTWrVOKTLTwJvOQ X-Received: by 2002:a17:902:3a5:: with SMTP id d34mr2568796pld.174.1553162446785; Thu, 21 Mar 2019 03:00:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553162446; cv=none; d=google.com; s=arc-20160816; b=dln0lH4ZQr+fNNu03jOLTUStdAa+tuAxeIGBeD1Y6eNw+GEXPielWaw5Koq7hE3jpJ y7/Ft5mclsw2uBu0A1PYyFsVJJPupCkWn51WW/3qCjhOwIavOHU8vcFjGUylDPmO5xTU 1+b5bWOiGdGhfWL3YQ/vXalhyu9XT/1CVi6ff/ANvHxBySFQ6ZGXBhFzWeJiYDhxRRNa icauUvXIt6HF12sccywtwFojfs7lEg0OruTjclQlUqnq8Z6qGqYrvzheT2g3KDfjdlIZ LQ7haH3e47PDcBEpQI28yiDxnQAIBBErr+IHhu+NDHbkya5oqzAiNZzN7pKs7gbPxIsA 7LEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=S0Rk5/1Z0zRlMch9nII8wu6ist2jo/kfY+1bHZOv1OM=; b=ly42m1hlhTOZ3gmmV1tFXLNssoyaq1pj5KC1TFCm4latnIfITHvXYYrR+3VmqTW1Ag MBrv1YSWqwAqcz+ZBSaP4t+jRSKum1OUO5YJRSvI+cJhGV94Kt2Tv8c/xZxfuPh+gTBR 5BZfw1Qga2jdkduJc/StXzHo9ztpGCLg5bRInkXAD3PXkvjSF5etmmfIhbvdcNcC76jI P7vtN3Ooex9lqRGVyZwlEwPOYDxoPqBTIfGD8dqxLXKrsp7ZTyd+sTbenbYgCY3x82GO KSs3enFJRUJYLgaIL9PwjpKTrrP904e21CUhO8V8Tph/dQygWEoDkRqZvCCL1bd3Rp/+ +jCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jv1rNva0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 124si3940411pfw.148.2019.03.21.03.00.46; Thu, 21 Mar 2019 03:00:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jv1rNva0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728336AbfCUKAp (ORCPT + 31 others); Thu, 21 Mar 2019 06:00:45 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39232 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728284AbfCUKAk (ORCPT ); Thu, 21 Mar 2019 06:00:40 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2LA0Omj006882; Thu, 21 Mar 2019 05:00:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553162424; bh=S0Rk5/1Z0zRlMch9nII8wu6ist2jo/kfY+1bHZOv1OM=; h=From:To:CC:Subject:Date; b=jv1rNva0ashr7xk3/pzyiPJY9ub6+HmI+lrRM1si7LjeMzvu6xShIyAvNx5n8rg+y u8ns9j1qUeZoPAUPD9tjqdOo8T3XsHH+kGHsh+W56lEfPsfDWZCbBKqS+PabBjjJTr 6NpxHZR9GImHRstVp3Nr2oCaWzDM8idXidPYjUJo= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2LA0OMT068964 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Mar 2019 05:00:24 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 21 Mar 2019 05:00:23 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Thu, 21 Mar 2019 05:00:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2LA0KO6014903; Thu, 21 Mar 2019 05:00:20 -0500 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Bjorn Helgaas , Gustavo Pimentel , Marc Zyngier CC: Kishon Vijay Abraham I , Jingoo Han , , , Subject: [PATCH v5 0/8] PCI: DWC/Keystone: MSI configuration cleanup Date: Thu, 21 Mar 2019 15:29:19 +0530 Message-ID: <20190321095927.7058-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series tries to address the comments discussed in [1] w.r.t removing Keystone specific callbacks defined in dw_pcie_host_ops. This series also tries to cleanup the Keystone interrupt handling part. Changes from v4: *) Removed legacy interrupt cleanup patch which uses hierarchy IRQ domain since TI platform uses edge interrupt for legacy interrupt. This will be deferred till I get more details from HW team. Changes from v3: *) Uses hierarchy IRQ domain for legacy interrupts since there is 1:1 mapping between legacy interrupt and GIC IRQ. (MSI still depends on the order of IRQs populated in dt). Changes from v2: *) Removed patch that modifies ks_pcie_legacy_irq_handler() to check the IRQ_STATUS of INTA/B/C/D. Lorenzo's comment to create a matrix LinuxIRQ x INTx will be added in AM654x PCIe support series *) ks_pcie_legacy_irq_handler() is made to use hwirq to get IRQ offset instead of virq. *) default msi_irq_chip is assigned in dw_pcie_host_init() once keystone assigns its msi_irq_chip *) Fixed other minor comments from Lorenzo and Bjorn Changes from v1: *) Removed "PCI: keystone: Use "dummy_irq_chip" instead of new irqchip for legacy interrupt handling" from the patch series. It should be handled differently. *) Added Gustavo's ACKed by and fixed a commit message. [1] -> https://patchwork.kernel.org/patch/10681587/ Kishon Vijay Abraham I (8): PCI: keystone: Cleanup interrupt related macros PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Cleanup ks_pcie_msi_irq_handler PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: dwc: Do not write to MSI control registers if the platform doesn't use it drivers/pci/controller/dwc/pci-keystone.c | 365 ++++++++++-------- .../pci/controller/dwc/pcie-designware-host.c | 78 ++-- drivers/pci/controller/dwc/pcie-designware.h | 6 +- 3 files changed, 233 insertions(+), 216 deletions(-) -- 2.17.1