From patchwork Wed Oct 5 16:50:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4538 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9040123EF9 for ; Wed, 5 Oct 2011 16:51:16 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 5D2BBA18BE0 for ; Wed, 5 Oct 2011 16:51:16 +0000 (UTC) Received: by yxm34 with SMTP id 34so2543464yxm.11 for ; Wed, 05 Oct 2011 09:51:15 -0700 (PDT) Received: by 10.223.45.140 with SMTP id e12mr3785282faf.27.1317833475418; Wed, 05 Oct 2011 09:51:15 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.23.170 with SMTP id n10cs98625laf; Wed, 5 Oct 2011 09:51:15 -0700 (PDT) Received: by 10.213.13.141 with SMTP id c13mr609866eba.25.1317833474856; Wed, 05 Oct 2011 09:51:14 -0700 (PDT) Received: from eu1sys200aog113.obsmtp.com (eu1sys200aog113.obsmtp.com. [207.126.144.135]) by mx.google.com with SMTP id m12si247283eeh.113.2011.10.05.09.51.08 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 05 Oct 2011 09:51:14 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.135; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP; Wed, 05 Oct 2011 16:51:14 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 52C07A9; Wed, 5 Oct 2011 16:42:35 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3C37A76B; Wed, 5 Oct 2011 16:51:04 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id CA50224C075; Wed, 5 Oct 2011 18:50:54 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 5 Oct 2011 18:51:03 +0200 From: Linus Walleij To: Samuel Ortiz , Cc: Lee Jones , Linus Walleij Subject: [PATCH 2/2] mfd/dbx500-prcmu: refactor request_clock() functions Date: Wed, 5 Oct 2011 18:50:58 +0200 Message-ID: <1317833458-747-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij This refactors the mfd/dbx500-prcmu drivers to use a switch() statement rather than nested if/else-construction. Signed-off-by: Linus Walleij --- Patch created in response to Samuel Ortiz' review comment on the patch named "mfd/db8500-prcmu: add accessors for PLL and SGA clock" --- drivers/mfd/db5500-prcmu.c | 21 ++++++++++++--------- drivers/mfd/db8500-prcmu.c | 19 +++++++++++-------- 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c index 47fd0e9..f2c79b2 100644 --- a/drivers/mfd/db5500-prcmu.c +++ b/drivers/mfd/db5500-prcmu.c @@ -588,20 +588,23 @@ unlock_and_return: */ int db5500_prcmu_request_clock(u8 clock, bool enable) { - if (clock < PRCMU_NUM_REG_CLOCKS) - return request_reg_clock(clock, enable); - else if (clock == PRCMU_TIMCLK) + switch(clock) { + case PRCMU_TIMCLK: return request_timclk(enable); - else if (clock == PRCMU_PLLSOC0) + case PRCMU_PLLSOC0: return request_pll(DB5500_PLL_SOC0, enable); - else if (clock == PRCMU_PLLSOC1) + case PRCMU_PLLSOC1: return request_pll(DB5500_PLL_SOC1, enable); - else if (clock == PRCMU_PLLDDR) + case PRCMU_PLLDDR: return request_pll(DB5500_PLL_DDR, enable); - else if (clock == PRCMU_SYSCLK) + case PRCMU_SYSCLK: return request_sysclk(enable); - else - return -EINVAL; + default: + break; + } + if (clock < PRCMU_NUM_REG_CLOCKS) + return request_reg_clock(clock, enable); + return -EINVAL; } /* This function should only be called while mb0_transfer.lock is held. */ diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 98da431..e996d11 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -1433,18 +1433,21 @@ static int request_sga_clock(u8 clock, bool enable) */ int db8500_prcmu_request_clock(u8 clock, bool enable) { - if (clock == PRCMU_SGACLK) + switch(clock) { + case PRCMU_SGACLK: return request_sga_clock(clock, enable); - else if (clock < PRCMU_NUM_REG_CLOCKS) - return request_reg_clock(clock, enable); - else if (clock == PRCMU_TIMCLK) + case PRCMU_TIMCLK: return request_timclk(enable); - else if (clock == PRCMU_SYSCLK) + case PRCMU_SYSCLK: return request_sysclk(enable); - else if (clock == PRCMU_PLLSOC1) + case PRCMU_PLLSOC1: return request_pll(clock, enable); - else - return -EINVAL; + default: + break; + } + if (clock < PRCMU_NUM_REG_CLOCKS) + return request_reg_clock(clock, enable); + return -EINVAL; } int db8500_prcmu_config_esram0_deep_sleep(u8 state)