From patchwork Tue Mar 20 20:22:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob X-Patchwork-Id: 7368 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 10D1A23DC3 for ; Tue, 20 Mar 2012 20:23:12 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id BE681A18152 for ; Tue, 20 Mar 2012 20:23:11 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so671092iag.11 for ; Tue, 20 Mar 2012 13:23:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=FcvQbxOPHZw/UCgdlweHP0GUMFLtiUNSkyA6YldLYvI=; b=pq24EIcI2/OjojkPDqckSjR4+FJPNCk2pylVinoum1GYkaBl459iOxxcjdi+hDD99P RIcymrPh4MQePjAgIrxGuJIQgnCQpz+eTj6ghIbky8pYG8v/Dv6wM/hp3L6kWJXzrnv7 GYaxHGmjvH94x8PA12QBLyeHWFtDQxDpKujKevVP31De42laMtJfsQw+6nJtiaUuapef H8yVV7ruewedo3hrdAl7nbgR7X0Z/7VURB5KXdUIN3LeQROYh4Zxx28T8/YQ9C8wnsm4 jibKA7HbW5Ri/AYB6qTTKqjx4Wrmq8kThMzySGQzFQpE0jX6KikKST4eH1YdZpH4DFpl kvIA== Received: by 10.42.72.130 with SMTP id o2mr957372icj.8.1332274991545; Tue, 20 Mar 2012 13:23:11 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.203.79 with SMTP id fh15csp12145ibb; Tue, 20 Mar 2012 13:23:11 -0700 (PDT) Received: by 10.229.136.195 with SMTP id s3mr585270qct.60.1332274990461; Tue, 20 Mar 2012 13:23:10 -0700 (PDT) Received: from mail-qc0-f178.google.com (mail-qc0-f178.google.com [209.85.216.178]) by mx.google.com with ESMTPS id l7si1074534qcw.160.2012.03.20.13.23.10 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Mar 2012 13:23:10 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) client-ip=209.85.216.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.178 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) smtp.mail=rob.lee@linaro.org Received: by mail-qc0-f178.google.com with SMTP id e14so250671qcs.37 for ; Tue, 20 Mar 2012 13:23:10 -0700 (PDT) Received: by 10.229.137.20 with SMTP id u20mr564345qct.64.1332274986936; Tue, 20 Mar 2012 13:23:06 -0700 (PDT) Received: from localhost.localdomain ([216.59.27.113]) by mx.google.com with ESMTPS id n8sm4392976qan.12.2012.03.20.13.23.03 (version=SSLv3 cipher=OTHER); Tue, 20 Mar 2012 13:23:06 -0700 (PDT) From: Robert Lee To: len.brown@intel.com Cc: akpm@linux-foundation.org, rjw@sisk.pl, khilman@ti.com, robherring2@gmail.com, Baohua.Song@csr.com, amit.kucheria@linaro.org, nicolas.ferre@atmel.com, linux@maxim.org.za, kgene.kim@samsung.com, amit.kachhap@linaro.org, magnus.damm@gmail.com, nsekhar@ti.com, daniel.lezcano@linaro.org, mturquette@linaro.org, vincent.guittot@linaro.org, arnd.bergmann@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-dev@lists.linaro.org, patches@linaro.org, deepthi@linux.vnet.ibm.com, broonie@opensource.wolfsonmicro.com, nicolas.pitre@linaro.org, linux@arm.linux.org.uk, jean.pihet@newoldbits.com, venki@google.com, ccross@google.com, g.trinabh@gmail.com, kernel@wantstofly.org, lethal@linux-sh.org, jon-hunter@ti.com, tony@atomide.com, linux-omap@vger.kernel.org, linux-sh@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v8 3/8] ARM: kirkwood: Consolidate time keeping and irq enable Date: Tue, 20 Mar 2012 15:22:44 -0500 Message-Id: <1332274969-15782-4-git-send-email-rob.lee@linaro.org> X-Mailer: git-send-email 1.7.9.4 In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org> References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org> X-Gm-Message-State: ALoCoQliU4qkY/Xh/pEchbRvJytHxSiijNc2htA0dt6fz6uRHUZOUCG/u76kO2RzdBEyMG7Yuraz Enable core cpuidle timekeeping and irq enabling and remove that handling from this code. Signed-off-by: Robert Lee Reviewed-by: Kevin Hilman Reviewed-by: Daniel Lezcano Acked-by: Jean Pihet --- arch/arm/mach-kirkwood/cpuidle.c | 72 +++++++++++--------------------------- 1 file changed, 21 insertions(+), 51 deletions(-) diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c index 7088180..0f17109 100644 --- a/arch/arm/mach-kirkwood/cpuidle.c +++ b/arch/arm/mach-kirkwood/cpuidle.c @@ -20,77 +20,47 @@ #include #include #include +#include #include #define KIRKWOOD_MAX_STATES 2 -static struct cpuidle_driver kirkwood_idle_driver = { - .name = "kirkwood_idle", - .owner = THIS_MODULE, -}; - -static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device); - /* Actual code that puts the SoC in different idle states */ static int kirkwood_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct timeval before, after; - int idle_time; - - local_irq_disable(); - do_gettimeofday(&before); - if (index == 0) - /* Wait for interrupt state */ - cpu_do_idle(); - else if (index == 1) { - /* - * Following write will put DDR in self refresh. - * Note that we have 256 cycles before DDR puts it - * self in self-refresh, so the wait-for-interrupt - * call afterwards won't get the DDR from self refresh - * mode. - */ - writel(0x7, DDR_OPERATION_BASE); - cpu_do_idle(); - } - do_gettimeofday(&after); - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - /* Update last residency */ - dev->last_residency = idle_time; + writel(0x7, DDR_OPERATION_BASE); + cpu_do_idle(); return index; } +static struct cpuidle_driver kirkwood_idle_driver = { + .name = "kirkwood_idle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, + .states[0] = ARM_CPUIDLE_WFI_STATE, + .states[1] = { + .enter = kirkwood_enter_idle, + .exit_latency = 10, + .target_residency = 100000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "DDR SR", + .desc = "WFI and DDR Self Refresh", + }, + .state_count = KIRKWOOD_MAX_STATES, +}; + +static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device); + /* Initialize CPU idle by registering the idle states */ static int kirkwood_init_cpuidle(void) { struct cpuidle_device *device; - struct cpuidle_driver *driver = &kirkwood_idle_driver; device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id()); device->state_count = KIRKWOOD_MAX_STATES; - driver->state_count = KIRKWOOD_MAX_STATES; - - /* Wait for interrupt state */ - driver->states[0].enter = kirkwood_enter_idle; - driver->states[0].exit_latency = 1; - driver->states[0].target_residency = 10000; - driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID; - strcpy(driver->states[0].name, "WFI"); - strcpy(driver->states[0].desc, "Wait for interrupt"); - - /* Wait for interrupt and DDR self refresh state */ - driver->states[1].enter = kirkwood_enter_idle; - driver->states[1].exit_latency = 10; - driver->states[1].target_residency = 10000; - driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID; - strcpy(driver->states[1].name, "DDR SR"); - strcpy(driver->states[1].desc, "WFI and DDR Self Refresh"); cpuidle_register_driver(&kirkwood_idle_driver); if (cpuidle_register_device(device)) {