From patchwork Tue Nov 20 11:45:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 12985 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0641B23FC0 for ; Tue, 20 Nov 2012 11:46:25 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A9B1BA182AD for ; Tue, 20 Nov 2012 11:46:24 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id t4so1639056iag.11 for ; Tue, 20 Nov 2012 03:46:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=/6fZcSCcjaq9YC3Ca7yjMfrRmX/UM4z2KplcH5KId8k=; b=Q597KSBq6KlBmwroB6hiFWIIlNt1hriixvoQfint4oK3+JWGsmTbrxXRVThgYT1nW8 SPndIDdsoRc6vkyqI1LgGytZY0Oywxk90mkotOHiBC/ZGLjBrltE47KR5NXTpuClUFuc FyxHOwGeVhtJUSadNK7wJSmsFvVBricRi59Hzm8I+yH4sxPpIjVSCOYJjhoCzDM4PZyI KRRKGM1lAYFzNsBdj8Tu+Utc3r727XNVY5Iku3LZkqMjBmVPS02wX4B29LnJ4pSqr91O Lfs0RbyZTgcpy6WGlYa14JNnM9wY012iWPxJveaEVCxD2OVARuoCtWCDbs5a1+DVMpAE DizA== Received: by 10.50.186.199 with SMTP id fm7mr9491199igc.62.1353411984450; Tue, 20 Nov 2012 03:46:24 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp304885igt; Tue, 20 Nov 2012 03:46:23 -0800 (PST) Received: by 10.14.1.69 with SMTP id 45mr33598556eec.23.1353411982765; Tue, 20 Nov 2012 03:46:22 -0800 (PST) Received: from eu1sys200aog104.obsmtp.com (eu1sys200aog104.obsmtp.com [207.126.144.117]) by mx.google.com with SMTP id i42si14312614eem.40.2012.11.20.03.46.13 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 03:46:22 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.117 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.117; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.117 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob104.postini.com ([207.126.147.11]) with SMTP ID DSNKUKtthaREYYN2weQkSPo7UaOhiefx2u9m@postini.com; Tue, 20 Nov 2012 11:46:22 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AC89D13A; Tue, 20 Nov 2012 11:46:02 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 146DD2BC3; Tue, 20 Nov 2012 11:46:02 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id C632A24C07C; Tue, 20 Nov 2012 12:45:55 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 20 Nov 2012 12:46:00 +0100 From: Linus Walleij To: , , Shiraz Hashim , Viresh Kumar Cc: Stephen Warren , Anmar Oueja , Grant Likely , Linus Walleij Subject: [PATCH] gpiolib: let gpiochip_add_pin_range() specify offset Date: Tue, 20 Nov 2012 12:45:53 +0100 Message-ID: <1353411953-27423-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQl5HEJ4YXa0sZnA4EGRiz2bh0820spSC0Nz00hcRmrBrz3QnVplmetQlD6QBBGWlxwa5C5I From: Linus Walleij Like with commit 3c739ad0df5eb41cd7adad879eda6aa09879eb76 it is not always enough to specify all the pins of a gpio_chip from offset zero to be added to a pin map range, since the mapping from GPIO to pin controller may not be linear at all, but need to be broken into a few consecutive sub-ranges or 1-pin entries for complicated cases. The ranges may also be sparse. This alters the signature of the function to accept offsets into both the GPIO-chip local pinspace and the pin controller local pinspace. Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib.c | 18 ++++++++++++++++-- include/asm-generic/gpio.h | 6 ++++-- include/linux/gpio.h | 3 ++- 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index c5f6500..0b08d27 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1187,8 +1187,18 @@ EXPORT_SYMBOL_GPL(gpiochip_find); #ifdef CONFIG_PINCTRL +/** + * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping + * @chip: the gpiochip to add the range for + * @pinctrl_name: the dev_name() of the pin controller to map to + * @offset: the start offset in the current gpio_chip number space + * @pin_base: the start offset in the pin controller number space + * @npins: the number of pins from the offset of each pin space (GPIO and + * pin controller) to accumulate in this range + */ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int pin_base, unsigned int npins) + unsigned int offset, unsigned int pin_base, + unsigned int npins) { struct gpio_pin_range *pin_range; @@ -1200,7 +1210,7 @@ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, } pin_range->range.name = chip->label; - pin_range->range.base = chip->base; + pin_range->range.base = chip->base + offset; pin_range->range.pin_base = pin_base; pin_range->range.npins = npins; pin_range->pctldev = find_pinctrl_and_add_gpio_range(pinctl_name, @@ -1212,6 +1222,10 @@ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, } EXPORT_SYMBOL_GPL(gpiochip_add_pin_range); +/** + * gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings + * @chip: the chip to remove all the mappings for + */ void gpiochip_remove_pin_ranges(struct gpio_chip *chip) { struct gpio_pin_range *pin_range, *tmp; diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 2b84fc3..ec58fdb 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -283,14 +283,16 @@ struct gpio_pin_range { }; int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int pin_base, unsigned int npins); + unsigned int offset, unsigned int pin_base, + unsigned int npins); void gpiochip_remove_pin_ranges(struct gpio_chip *chip); #else static inline int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int pin_base, unsigned int npins) + unsigned int offset, unsigned int pin_base, + unsigned int npins) { return 0; } diff --git a/include/linux/gpio.h b/include/linux/gpio.h index 7ba2762..99861c6 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -233,7 +233,8 @@ static inline int irq_to_gpio(unsigned irq) static inline int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int pin_base, unsigned int npins) + unsigned int offset, unsigned int pin_base, + unsigned int npins) { WARN_ON(1); return -EINVAL;