From patchwork Tue Nov 20 14:04:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13003 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8874C23FC9 for ; Tue, 20 Nov 2012 14:05:19 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 31541A191A2 for ; Tue, 20 Nov 2012 14:05:19 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so8184274iej.11 for ; Tue, 20 Nov 2012 06:05:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=Nwv4MhQr0jrkSLTUv8r5LMbpXPKBfLVpF7NuOOA7mWo=; b=BlBQ9pYDz/HxejQbakAqTqV8ceKFACgHcqCV1TPgNHvxc+uWmqV8FOtBG06XMoChMX 8Hy3cKff6NVqk8Rjq4RI2ld+s6TTcvYKbRa/NZyCwWzLpl0BBNaT1kavrbDXNO+mOpBX puSjCQ5EdS9E0YkPVTKK6eTJctZb6XsxoViE8jx03gwIor9KP+WZbbKZWCSQL8IhmA+2 I496cVjzzFsrnykBYj91Qdhhk4LqC4aWHB6fCVHtyV+d/oUfu3VOQ7NcCPv9OEjNfwPl zNT1sB2SCKTC0T+9qtV9WIzfT4AWZ4PMvRFzkGF3+D1z+Hxo8VdSHaUmEJEC0bmsv2G2 whXA== Received: by 10.50.213.34 with SMTP id np2mr10031910igc.57.1353420318669; Tue, 20 Nov 2012 06:05:18 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp322374igt; Tue, 20 Nov 2012 06:05:18 -0800 (PST) Received: by 10.14.205.65 with SMTP id i41mr34597664eeo.2.1353420317486; Tue, 20 Nov 2012 06:05:17 -0800 (PST) Received: from eu1sys200aog117.obsmtp.com (eu1sys200aog117.obsmtp.com [207.126.144.143]) by mx.google.com with SMTP id c2si21753229eeo.71.2012.11.20.06.05.10 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 06:05:17 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.143; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKUKuOFv/tDq1Rycc26EVPKzicoeFBVtIY@postini.com; Tue, 20 Nov 2012 14:05:17 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 87C3D3C; Tue, 20 Nov 2012 14:04:32 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 9D81961; Tue, 20 Nov 2012 09:12:07 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id EBB9F24C2F7; Tue, 20 Nov 2012 15:04:55 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 20 Nov 2012 15:05:02 +0100 From: Linus Walleij To: , , Shiraz Hashim , Viresh Kumar Cc: Stephen Warren , Anmar Oueja , Grant Likely , Linus Walleij Subject: [PATCH 6/7] pinctrl/u300/coh901: let the gpio_chip register the range Date: Tue, 20 Nov 2012 15:04:58 +0100 Message-ID: <1353420298-18139-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkAtsUmv49oAzP1mMvNZv/hpdfKpXE6gvTAgUZ4eNuhHgp9JPrBw8/jCMnYd5lpLG3N3m/Y From: Linus Walleij Instead of having the pinctrl driver register the GPIO range for the gpio_chip, making it necessary to instantiate the pin controller from the GPIO driver and pass the GPIO chip as platform data, now let the GPIO chip driver register it's own ranges and have the pinctrl driver look up the GPIO chip from the pinctrl core as necessary. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-coh901.c | 47 ++++++++++++++++++++++++++++++++-- drivers/pinctrl/pinctrl-u300.c | 55 +++------------------------------------- 2 files changed, 49 insertions(+), 53 deletions(-) diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 1144dcd..0457430 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -658,6 +658,36 @@ static inline void u300_gpio_free_ports(struct u300_gpio *gpio) } } +/* + * Here we map a GPIO in the local gpio_chip pin space to a pin in + * the local pinctrl pin space. The pin controller used is + * pinctrl-u300. + */ +struct coh901_pinpair { + unsigned int offset; + unsigned int pin_base; +}; + +#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } + +static struct coh901_pinpair coh901_pintable[] = { + COH901_PINRANGE(10, 426), + COH901_PINRANGE(11, 180), + COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ + COH901_PINRANGE(13, 179), + COH901_PINRANGE(14, 178), + COH901_PINRANGE(16, 194), + COH901_PINRANGE(17, 193), + COH901_PINRANGE(18, 192), + COH901_PINRANGE(19, 191), + COH901_PINRANGE(20, 186), + COH901_PINRANGE(21, 185), + COH901_PINRANGE(22, 184), + COH901_PINRANGE(23, 183), + COH901_PINRANGE(24, 182), + COH901_PINRANGE(25, 181), +}; + static int __init u300_gpio_probe(struct platform_device *pdev) { struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); @@ -786,16 +816,29 @@ static int __init u300_gpio_probe(struct platform_device *pdev) goto err_no_chip; } - /* Spawn pin controller device as child of the GPIO, pass gpio chip */ - plat->pinctrl_device->dev.platform_data = &gpio->chip; + /* Spawn pin controller device as child of the GPIO */ err = platform_device_register(plat->pinctrl_device); if (err) goto err_no_pinctrl; + /* + * Add pinctrl pin ranges, the pin controller must be registered + * at this point + */ + for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { + struct coh901_pinpair *p = &coh901_pintable[i]; + + err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", + p->offset, p->pin_base, 1); + if (err) + goto err_no_range; + } + platform_set_drvdata(pdev, gpio); return 0; +err_no_range: err_no_pinctrl: err = gpiochip_remove(&gpio->chip); err_no_chip: diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index d756cce..b84de03 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1011,51 +1011,11 @@ static struct pinmux_ops u300_pmx_ops = { .disable = u300_pmx_disable, }; -/* - * GPIO ranges handled by the application-side COH901XXX GPIO controller - * Very many pins can be converted into GPIO pins, but we only list those - * that are useful in practice to cut down on tables. - */ -#define U300_GPIO_RANGE(a, b, c) { .name = "COH901XXX", .id = a, .base= a, \ - .pin_base = b, .npins = c } - -static struct pinctrl_gpio_range u300_gpio_ranges[] = { - U300_GPIO_RANGE(10, 426, 1), - U300_GPIO_RANGE(11, 180, 1), - U300_GPIO_RANGE(12, 165, 1), /* MS/MMC card insertion */ - U300_GPIO_RANGE(13, 179, 1), - U300_GPIO_RANGE(14, 178, 1), - U300_GPIO_RANGE(16, 194, 1), - U300_GPIO_RANGE(17, 193, 1), - U300_GPIO_RANGE(18, 192, 1), - U300_GPIO_RANGE(19, 191, 1), - U300_GPIO_RANGE(20, 186, 1), - U300_GPIO_RANGE(21, 185, 1), - U300_GPIO_RANGE(22, 184, 1), - U300_GPIO_RANGE(23, 183, 1), - U300_GPIO_RANGE(24, 182, 1), - U300_GPIO_RANGE(25, 181, 1), -}; - -static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) { - struct pinctrl_gpio_range *range; - - range = &u300_gpio_ranges[i]; - if (pin >= range->pin_base && - pin <= (range->pin_base + range->npins - 1)) - return range; - } - return NULL; -} - static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { - struct pinctrl_gpio_range *range = u300_match_gpio_range(pin); + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(pctldev, pin); /* We get config for those pins we CAN get it for and that's it */ if (!range) @@ -1069,7 +1029,8 @@ static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long config) { - struct pinctrl_gpio_range *range = u300_match_gpio_range(pin); + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(pctldev, pin); int ret; if (!range) @@ -1105,8 +1066,6 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev) { struct u300_pmx *upmx; struct resource *res; - struct gpio_chip *gpio_chip = dev_get_platdata(&pdev->dev); - int i; /* Create state holders etc for this driver */ upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL); @@ -1129,12 +1088,6 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev) return -EINVAL; } - /* We will handle a range of GPIO pins */ - for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) { - u300_gpio_ranges[i].gc = gpio_chip; - pinctrl_add_gpio_range(upmx->pctl, &u300_gpio_ranges[i]); - } - platform_set_drvdata(pdev, upmx); dev_info(&pdev->dev, "initialized U300 pin control driver\n");