From patchwork Fri Nov 23 00:49:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 13088 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1565F23E13 for ; Fri, 23 Nov 2012 00:53:29 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 967CEA1804B for ; Fri, 23 Nov 2012 00:53:28 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id c10so1226114ieb.11 for ; Thu, 22 Nov 2012 16:53:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=El1rkNr3e927FjI/rCbsbZMZJ/i4mdMxhto/RGJk6HI=; b=i7z6ygcIN237MVJXJkLM7zcRRrAllHHT+A96p7WpxMMQQRgEtBm4OMuLNBp6Iap953 G8K09F9c2i5jEM1BvWldfGGtBeFKeAIp5OgFSipsv5fOk63dYXMfXq4Uk5/gi1NeIIV9 Nut81RYK1YcN/d8k5WxZdKpa8cu4dJYlRa8HkzKFTtOc48RMlCNWLf1tUX9MJITykYCt a9F4fjENBhr5wJpms41/4oSv/K8nwJUtIaiFLPNxbk0lGd/ShjS+Xg/j5oAzLahQe9DN igvDOAR+J7IMcHAUiwHEEhn9HqZkmhHK05hX0j2JIRP25daWyffoi1o7576n7jOZqP5B K+1g== Received: by 10.43.7.132 with SMTP id oo4mr1903768icb.6.1353632008052; Thu, 22 Nov 2012 16:53:28 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp282371igt; Thu, 22 Nov 2012 16:53:27 -0800 (PST) Received: by 10.60.25.106 with SMTP id b10mr701682oeg.20.1353632007071; Thu, 22 Nov 2012 16:53:27 -0800 (PST) Received: from mail-ob0-f170.google.com (mail-ob0-f170.google.com [209.85.214.170]) by mx.google.com with ESMTPS id p7si4253897obj.166.2012.11.22.16.53.26 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 16:53:27 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.170 is neither permitted nor denied by best guess record for domain of anton.vorontsov@linaro.org) client-ip=209.85.214.170; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.170 is neither permitted nor denied by best guess record for domain of anton.vorontsov@linaro.org) smtp.mail=anton.vorontsov@linaro.org Received: by mail-ob0-f170.google.com with SMTP id wp18so7745782obc.15 for ; Thu, 22 Nov 2012 16:53:26 -0800 (PST) Received: by 10.60.32.193 with SMTP id l1mr1573690oei.114.1353632006799; Thu, 22 Nov 2012 16:53:26 -0800 (PST) Received: from localhost (ip-64-134-239-153.public.wayport.net. [64.134.239.153]) by mx.google.com with ESMTPS id q4sm4476274obz.3.2012.11.22.16.53.24 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 16:53:26 -0800 (PST) From: Anton Vorontsov To: Andrew Morton Cc: Russell King , Jason Wessel , John Stultz , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, patches@linaro.org, kernel-team@android.com Subject: [PATCH 01/10] ARM: mach-rpc: Don't register FIQs with genirq Date: Thu, 22 Nov 2012 16:49:54 -0800 Message-Id: <1353631803-4853-1-git-send-email-anton.vorontsov@linaro.org> X-Mailer: git-send-email 1.8.0 In-Reply-To: <20121123003849.GA973@lizard.mcd25758.sjc.wayport.net> References: <20121123003849.GA973@lizard.mcd25758.sjc.wayport.net> X-Gm-Message-State: ALoCoQkm01sNMrVEyY5lb1ph2e4BVpRaUF4QmGbYMV5nn9VVDrgAHx9WFdsydX2+nxcH3fWfRr1S mach-rps registers FIQ controller with genirq, which makes no sense: these FIQs cannot be routed to IRQs, so there is no need to register it with genirq. This effectively makes FIQ_START irrelevant. Signed-off-by: Anton Vorontsov --- arch/arm/mach-rpc/dma.c | 4 ++-- arch/arm/mach-rpc/include/mach/irqs.h | 5 +++++ arch/arm/mach-rpc/irq.c | 19 ++++--------------- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 85883b2..4a525be 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c @@ -289,13 +289,13 @@ static void floppy_enable_dma(unsigned int chan, dma_t *dma) set_fiq_handler(fiqhandler_start, fiqhandler_length); set_fiq_regs(®s); - enable_fiq(fdma->fiq); + iomd_unmask_fiq(fdma->fiq); } static void floppy_disable_dma(unsigned int chan, dma_t *dma) { struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); - disable_fiq(fdma->fiq); + iomd_mask_fiq(fdma->fiq); release_fiq(&fh); } diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h index 6868e17..f27ead1 100644 --- a/arch/arm/mach-rpc/include/mach/irqs.h +++ b/arch/arm/mach-rpc/include/mach/irqs.h @@ -37,6 +37,11 @@ #define FIQ_EXPANSIONCARD 6 #define FIQ_FORCE 7 +#ifndef __ASSEMBLY__ +extern void iomd_mask_fiq(int fiq); +extern void iomd_unmask_fiq(int fiq); +#endif + /* * This is the offset of the FIQ "IRQ" numbers */ diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 3e4fa84..a4221b3 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -89,30 +89,24 @@ static struct irq_chip iomd_dma_chip = { .irq_unmask = iomd_unmask_irq_dma, }; -static void iomd_mask_irq_fiq(struct irq_data *d) +void iomd_mask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val & ~mask, IOMD_FIQMASK); } -static void iomd_unmask_irq_fiq(struct irq_data *d) +void iomd_unmask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val | mask, IOMD_FIQMASK); } -static struct irq_chip iomd_fiq_chip = { - .irq_ack = iomd_mask_irq_fiq, - .irq_mask = iomd_mask_irq_fiq, - .irq_unmask = iomd_unmask_irq_fiq, -}; - extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; void __init rpc_init_irq(void) @@ -155,11 +149,6 @@ void __init rpc_init_irq(void) handle_level_irq); set_irq_flags(irq, flags); break; - - case 64 ... 71: - irq_set_chip(irq, &iomd_fiq_chip); - set_irq_flags(irq, IRQF_VALID); - break; } }