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Tue, 09 Apr 2013 08:37:04 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 47936F7; Tue, 9 Apr 2013 08:28:46 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AF171A53; Tue, 9 Apr 2013 08:36:53 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 02F21A8065; Tue, 9 Apr 2013 10:36:49 +0200 (CEST) Received: from lmenx30b.lme.st.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.279.5; Tue, 9 Apr 2013 10:36:52 +0200 From: Jean-Nicolas Graux To: Samuel Ortiz , Cc: Lee Jones , Jean-Nicolas Graux Subject: [PATCH 3/3] gpio: support stmpe1801 18 bits enhanced port expander Date: Tue, 9 Apr 2013 10:35:21 +0200 Message-ID: <1365496521-16880-3-git-send-email-jean-nicolas.graux@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1365496521-16880-1-git-send-email-jean-nicolas.graux@stericsson.com> References: <1365496521-16880-1-git-send-email-jean-nicolas.graux@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnPioONoZr4j1hOrVry9NcxiEUjkwm2+Sjx7GRQGimwXs3MRaK3N5qOVtHm4kJdifI7Ercd X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Provides support for 1801 variant of stmpe gpio port expanders. This chip has 18 gpios configurable as GPI, GPO, keypad matrix, special key or dedicated key function. Note that special/dedicated key function is not supported yet. Signed-off-by: Jean-Nicolas Graux --- drivers/gpio/gpio-stmpe.c | 52 ++++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c index 770476a..343dfe1 100644 --- a/drivers/gpio/gpio-stmpe.c +++ b/drivers/gpio/gpio-stmpe.c @@ -45,14 +45,25 @@ static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) return container_of(chip, struct stmpe_gpio, chip); } +static inline u8 stmpe_gpio_reg(struct stmpe *stmpe, u8 index, int offset) +{ + u8 reg; + if (stmpe->partnum == STMPE1801) + reg = stmpe->regs[index] + offset; + else + reg = stmpe->regs[index] - offset; + return reg; +} + static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) { struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); int ret; + u8 reg, mask; + reg = stmpe_gpio_reg(stmpe, STMPE_IDX_GPMR_LSB, offset / 8); + mask = 1 << (offset % 8); ret = stmpe_reg_read(stmpe, reg); if (ret < 0) return ret; @@ -65,8 +76,10 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; - u8 reg = stmpe->regs[which] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg, mask; + + reg = stmpe_gpio_reg(stmpe, which, offset / 8); + mask = 1 << (offset % 8); /* * Some variants have single register for gpio set/clear functionality. @@ -83,8 +96,10 @@ static int stmpe_gpio_direction_output(struct gpio_chip *chip, { struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg, mask; + + reg = stmpe_gpio_reg(stmpe, STMPE_IDX_GPDR_LSB, offset / 8); + mask = 1 << (offset % 8); stmpe_gpio_set(chip, offset, val); @@ -96,8 +111,10 @@ static int stmpe_gpio_direction_input(struct gpio_chip *chip, { struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg, mask; + + reg = stmpe_gpio_reg(stmpe, STMPE_IDX_GPDR_LSB, offset / 8); + mask = 1 << (offset % 8); return stmpe_set_bits(stmpe, reg, mask, 0); } @@ -177,6 +194,7 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) [REG_IE] = STMPE_IDX_IEGPIOR_LSB, }; int i, j; + u8 reg; for (i = 0; i < CACHE_NR_REGS; i++) { /* STMPE801 doesn't have RE and FE registers */ @@ -192,7 +210,8 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) continue; stmpe_gpio->oldregs[i][j] = new; - stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); + reg = stmpe_gpio_reg(stmpe, regmap[i], j); + stmpe_reg_write(stmpe, reg, new); } } @@ -232,18 +251,20 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev) { struct stmpe_gpio *stmpe_gpio = dev; struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); u8 status[num_banks]; int ret; int i; + bool lsb = stmpe->partnum == STMPE1801; + u8 statmsbreg = lsb ? stmpe->regs[STMPE_IDX_ISGPIOR_LSB] : + stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); if (ret < 0) return IRQ_NONE; for (i = 0; i < num_banks; i++) { - int bank = num_banks - i - 1; + int bank = lsb ? i : num_banks - i - 1; unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; unsigned int stat = status[i]; @@ -262,10 +283,11 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev) stmpe_reg_write(stmpe, statmsbreg + i, status[i]); - /* Edge detect register is not present on 801 */ - if (stmpe->partnum != STMPE801) - stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] - + i, status[i]); + /* Edge detect register is not present on 801 and 1801 */ + if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1801) + stmpe_reg_write(stmpe, + stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, + status[i]); } return IRQ_HANDLED;