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Thu, 16 May 2013 23:09:25 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c01::22d is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=2607:f8b0:400e:c01::22d; Received: by mail-pb0-f45.google.com with SMTP id mc8so3000613pbc.18 for ; Thu, 16 May 2013 23:09:25 -0700 (PDT) X-Received: by 10.68.217.135 with SMTP id oy7mr47084545pbc.133.1368770965339; Thu, 16 May 2013 23:09:25 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id t1sm10802497pab.12.2013.05.16.23.09.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 16 May 2013 23:09:24 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, patches@linaro.org Subject: [PATCH 1/2] clk: exynos5250: Update cpufreq related clocks for EXYNOS5250 Date: Fri, 17 May 2013 11:25:52 +0530 Message-Id: <1368770153-29041-2-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> References: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQliMMBeXXHXPwnLW51oC/mKdU1S0HtnGuTclVphXV3sR2yqgvIEbFfJEizinYHlnqKc/MLO X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22d is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos5250.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 5c97e75..05d099d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { }; struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { - MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), - MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), + MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), + MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), - MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), + MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),