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Thu, 16 May 2013 23:09:28 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.182 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=209.85.192.182; Received: by mail-pd0-f182.google.com with SMTP id 3so3030572pdj.13 for ; Thu, 16 May 2013 23:09:28 -0700 (PDT) X-Received: by 10.66.165.97 with SMTP id yx1mr17106796pab.82.1368770968586; Thu, 16 May 2013 23:09:28 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id t1sm10802497pab.12.2013.05.16.23.09.25 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 16 May 2013 23:09:27 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, patches@linaro.org Subject: [PATCH 2/2] clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock Date: Fri, 17 May 2013 11:25:53 +0530 Message-Id: <1368770153-29041-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> References: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQmWvYy9X1REIkBN9YJYQHAOEI5wS4KwSldEDfHH1lVovK9KXwd1+gjAAiT56xTeYSxhGat3 X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , 'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos5250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 05d099d..b6d79c0 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -155,7 +155,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = { /* list of all parent clock list */ PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; -PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; +PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };