From patchwork Thu Sep 26 09:54:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20578 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f72.google.com (mail-qa0-f72.google.com [209.85.216.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 207FB23A4E for ; Thu, 26 Sep 2013 09:55:24 +0000 (UTC) Received: by mail-qa0-f72.google.com with SMTP id j7sf914550qaq.11 for ; Thu, 26 Sep 2013 02:55:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=s4E3p++kFgGFWFg3j+5G3aw/ZbXqNoU7Pe6Cj46PS5Y=; b=YuD2B97M2zqrkRc1apNiv2zVYwIzFo7UpPgoOg3HwQbi/ykBvyoTTCMHWTpPR4mYws QjngQQDqYyQWw2DvwzOl0CxopXquk/Oksn/qra3O1FCYsw1r4q+QjFfbN55L5WBLnk6p qK4nVpXNdytFCnjm2CiJNTli7bWzq2loohhcsbVI1/1Ua3LKHcPd4uRhdGg9uSYaQxHZ PUIPFAGwX04o5uFESGQrR72b/9/vsILeiFZMkVw1AkOM0UTZ1aD400J1D86+kucrJTFg X8q8LI+852nbFa0jjHhNvd18lgKXt4DrXB1a0IxJRpPohmHZSV4ODqYcLLYeLT586S32 nRyw== X-Gm-Message-State: ALoCoQn+LJOKp2v3drs766vrLxYJ4rAsSFpcWxNvQkYmyApUWOH6C1LN0CINpP3eAzN/qRLk2a+R X-Received: by 10.236.147.18 with SMTP id s18mr15502yhj.28.1380189323968; Thu, 26 Sep 2013 02:55:23 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.35.244 with SMTP id l20ls845995qej.98.gmail; Thu, 26 Sep 2013 02:55:23 -0700 (PDT) X-Received: by 10.220.196.11 with SMTP id ee11mr17018vcb.96.1380189323866; Thu, 26 Sep 2013 02:55:23 -0700 (PDT) Received: from mail-ve0-f171.google.com (mail-ve0-f171.google.com [209.85.128.171]) by mx.google.com with ESMTPS id o5si174252vdw.141.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 02:55:23 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.171; Received: by mail-ve0-f171.google.com with SMTP id pa12so686776veb.16 for ; Thu, 26 Sep 2013 02:54:53 -0700 (PDT) X-Received: by 10.52.37.69 with SMTP id w5mr39835vdj.32.1380189293756; Thu, 26 Sep 2013 02:54:53 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp356361vcz; Thu, 26 Sep 2013 02:54:53 -0700 (PDT) X-Received: by 10.15.83.2 with SMTP id b2mr131861eez.28.1380189292406; Thu, 26 Sep 2013 02:54:52 -0700 (PDT) Received: from eu1sys200aog101.obsmtp.com (eu1sys200aog101.obsmtp.com [207.126.144.111]) by mx.google.com with SMTP id k2si721220eey.152.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 26 Sep 2013 02:54:52 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.111 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.111; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob101.postini.com ([207.126.147.11]) with SMTP ID DSNKUkQERc16rOvkt34iKzmieFBulm2F3KY9@postini.com; Thu, 26 Sep 2013 09:54:52 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D6206138; Thu, 26 Sep 2013 09:53:53 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 38CBD4A9B; Thu, 26 Sep 2013 09:41:07 +0000 (GMT) Received: from lmenx29l.lme.st.com (lmenx29l.lme.st.com [10.201.23.80] (may be forged)) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BNF32112 (AUTH lme00137); Thu, 26 Sep 2013 11:54:11 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, kernel@stlinux.com, Maxime Coquelin Subject: [PATCH v2 2/4] ARM: STi: Supply I2C configuration to STiH416 SoC Date: Thu, 26 Sep 2013 11:54:09 +0200 Message-Id: <1380189249-5821-1-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH416 SoC. Cc: Srinivas Kandagatla Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 35 +++++++++++++++++ arch/arm/boot/dts/stih416.dtsi | 65 ++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 0f246c9..b29ff4b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -97,6 +97,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -175,6 +193,23 @@ }; }; + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1a0326e..a3069a8 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -92,5 +93,69 @@ pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; }; };