From patchwork Thu Sep 26 09:54:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20579 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f71.google.com (mail-qe0-f71.google.com [209.85.128.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BC37D23A4E for ; Thu, 26 Sep 2013 09:55:31 +0000 (UTC) Received: by mail-qe0-f71.google.com with SMTP id a11sf753566qen.6 for ; Thu, 26 Sep 2013 02:55:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=XZgnRLuFctDZChdHWwVO4RPBueDwJyNkxaTm0cSNqUI=; b=nLw9Uq7dh08t3E2vLGRsxRka2xnG3zerRw1+qBpTMATAGyE7N2A25RydEQalcfUy3w phvR7OKDXczhbYuGYsd9Cx3OufcVDSmdiy3wCKqt9SGYqGKh+CwGi3Fpf9cXAW51uiCM GozAjmgv1PFNJaLHMgmlJs/tgmdlTF3XzmdS5RtB04oRR9GAI6oxDiTZFj6twvv+fxOn Aksl9/MExOA4BMZSDbzAKYjJI6W3LlsJyH7wSdcNFhkopDTd70Dvt6MuvKXKzRGmc9b1 FITSNuQs+HcfF+lxLuuotwTNLtlN8nWAadhMr7pqqeaAkrkxBf12qNh3W4Y0g4AriyFc /JTQ== X-Gm-Message-State: ALoCoQlTufqhTHsDzLFckDsF/Iq6g/ratEfpPHiDkwgHw60RuvId96vRk7Or6A4ipdBFkb9Z+0cr X-Received: by 10.236.167.138 with SMTP id i10mr5780yhl.9.1380189331627; Thu, 26 Sep 2013 02:55:31 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.16.6 with SMTP id b6ls872848qed.79.gmail; Thu, 26 Sep 2013 02:55:31 -0700 (PDT) X-Received: by 10.58.252.36 with SMTP id zp4mr60308vec.95.1380189331543; Thu, 26 Sep 2013 02:55:31 -0700 (PDT) Received: from mail-vc0-f173.google.com (mail-vc0-f173.google.com [209.85.220.173]) by mx.google.com with ESMTPS id vr9si187051vcb.51.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 02:55:31 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.173; Received: by mail-vc0-f173.google.com with SMTP id if17so650838vcb.4 for ; Thu, 26 Sep 2013 02:55:01 -0700 (PDT) X-Received: by 10.52.116.74 with SMTP id ju10mr44807vdb.20.1380189301433; Thu, 26 Sep 2013 02:55:01 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp356364vcz; Thu, 26 Sep 2013 02:55:00 -0700 (PDT) X-Received: by 10.14.218.5 with SMTP id j5mr52192eep.134.1380189300318; Thu, 26 Sep 2013 02:55:00 -0700 (PDT) Received: from eu1sys200aog118.obsmtp.com (eu1sys200aog118.obsmtp.com [207.126.144.145]) by mx.google.com with SMTP id l4si743067eew.71.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 26 Sep 2013 02:55:00 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.145; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKUkQET+RFacSf6TLe4/wonLblANNZBC+u@postini.com; Thu, 26 Sep 2013 09:55:00 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 075CEF5; Thu, 26 Sep 2013 09:54:04 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D29CC4A9E; Thu, 26 Sep 2013 09:41:16 +0000 (GMT) Received: from lmenx29l.lme.st.com (lmenx29l.lme.st.com [10.201.23.80] (may be forged)) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BNF32186 (AUTH lme00137); Thu, 26 Sep 2013 11:54:20 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, kernel@stlinux.com, Maxime Coquelin Subject: [PATCH v2 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Thu, 26 Sep 2013 11:54:18 +0200 Message-Id: <1380189258-5872-1-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH415 SoC. Cc: Srinivas Kandagatla Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 65 ++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..12598c5 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,69 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + st,glitches; + st,glitch-clk = <500>; + st,glitch-dat = <500>; + + status = "disabled"; + }; }; };