From patchwork Tue Oct 1 10:39:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 20717 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ye0-f198.google.com (mail-ye0-f198.google.com [209.85.213.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5A77923920 for ; Tue, 1 Oct 2013 10:40:00 +0000 (UTC) Received: by mail-ye0-f198.google.com with SMTP id m11sf6768246yen.1 for ; Tue, 01 Oct 2013 03:40:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=MEb8xGsT7ktZAvYD0sN/84/wvD9V+pZv+AH4tuAP4EU=; b=afOZKiWRRkYn56hWRa1IDLcac3iDrJ6izN6+cMuHtfpJa/2YvG1XBuAuNs/aM1NVkR pCHq0CI71ltIFy9WA+5x7bHNCMFUODBa9jz7Z+IUul6ufmh6jeXnnZWH0RTr/hCnLCc8 QN31fN3nL/UppFSFHMMmaLsst7Myd+63ed/ayj892QQUWJcvhhjOd+X+HZwAGKs25eDw DgPkRzohqolpXmqeA4UkIjg69S8JYEtiNjZsNSNQ8iAqYtuP/jyojXnp7CbCBcj1sUAu GuCD2We3yWpiJacgBEVIkJLjhReRsPqnDm7VJneld2XrzN2xrtuN7pXdeEiHojCmydpU tD2w== X-Received: by 10.236.142.38 with SMTP id h26mr665454yhj.57.1380624000173; Tue, 01 Oct 2013 03:40:00 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.11.179 with SMTP id r19ls18068qeb.76.gmail; Tue, 01 Oct 2013 03:40:00 -0700 (PDT) X-Received: by 10.221.64.17 with SMTP id xg17mr27141817vcb.5.1380624000060; Tue, 01 Oct 2013 03:40:00 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id o3si1180001ves.10.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Oct 2013 03:40:00 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id jy13so4964677veb.6 for ; Tue, 01 Oct 2013 03:40:00 -0700 (PDT) X-Gm-Message-State: ALoCoQnriLLLl7sGQmMjcPhdqjfd779h1ZJAGX+8Q+VYgWalAym0LyTrAFjB4qiAL3rFDecl+JTt X-Received: by 10.220.46.72 with SMTP id i8mr27768475vcf.10.1380623999955; Tue, 01 Oct 2013 03:39:59 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp7220vcz; Tue, 1 Oct 2013 03:39:59 -0700 (PDT) X-Received: by 10.14.218.197 with SMTP id k45mr45349097eep.32.1380623998312; Tue, 01 Oct 2013 03:39:58 -0700 (PDT) Received: from eu1sys200aog105.obsmtp.com (eu1sys200aog105.obsmtp.com [207.126.144.119]) by mx.google.com with SMTP id l4si4142772eew.341.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 01 Oct 2013 03:39:58 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.119 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.119; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKUkqmWEEJMnFTnsR5Tg0zuT33VbiKGAIh@postini.com; Tue, 01 Oct 2013 10:39:58 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CD99D351; Tue, 1 Oct 2013 10:38:58 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 00B124E83; Tue, 1 Oct 2013 10:26:12 +0000 (GMT) Received: from lmenx29l.bri.st.com (lmenx29l.bri.st.com [10.65.5.31]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BNP59699 (AUTH lme00137); Tue, 1 Oct 2013 12:39:18 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, kernel@stlinux.com, Maxime Coquelin Subject: [PATCH 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Tue, 1 Oct 2013 12:39:11 +0200 Message-Id: <1380623952-4252-4-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380623952-4252-1-git-send-email-maxime.coquelin@st.com> References: <1380623952-4252-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH415 SoC. Cc: Srinivas Kandagatla Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..eb4fccb 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; };