From patchwork Mon Oct 14 12:46:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime COQUELIN X-Patchwork-Id: 21003 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f70.google.com (mail-pb0-f70.google.com [209.85.160.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B183220DA3 for ; Mon, 14 Oct 2013 12:48:59 +0000 (UTC) Received: by mail-pb0-f70.google.com with SMTP id jt11sf13198093pbb.9 for ; Mon, 14 Oct 2013 05:48:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=ujtkpVNRd0tMdRYW8AUsGtvy0I1colAZ5EfL6KJq1os=; b=eeW/97b6S91qhBt0pefQ+YhzGtBRgfSbb9wYkOJ7v2mG16xh8WIXQLdDE2EPqqakEr EBdZT5ME02uinyq25TliBD/UtFKMFT5dSzSxCuronPRkeFgrTTPfu6QdR94jehMfmFEJ xbmT1ZDnHCxYiZ7xKXyCAD5ToGu9T0DKy3YyM0LLOQfEBUflLlgzxpuMD4HELcNgwbjx +DblqJMGOogXzgLPPSNTXTZmtbqJoWBzeLx9WN/u6TZH4W6Ew6kbY4ZqcJ/KRPMJBLH4 lqsnxr5x0008wsLFvmglvWfj3/DNzU4UGqzTniOMxmy5X3yLZIO/w+0uYyJ7F/d6S9A/ 8/kQ== X-Received: by 10.68.190.8 with SMTP id gm8mr2110307pbc.7.1381754939007; Mon, 14 Oct 2013 05:48:59 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.13.9 with SMTP id d9ls2198504qec.26.gmail; Mon, 14 Oct 2013 05:48:58 -0700 (PDT) X-Received: by 10.220.10.194 with SMTP id q2mr34376533vcq.2.1381754938880; Mon, 14 Oct 2013 05:48:58 -0700 (PDT) Received: from mail-vb0-f54.google.com (mail-vb0-f54.google.com [209.85.212.54]) by mx.google.com with ESMTPS id f20si21054232vcs.67.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 14 Oct 2013 05:48:58 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.54; Received: by mail-vb0-f54.google.com with SMTP id q14so4362790vbe.41 for ; Mon, 14 Oct 2013 05:48:58 -0700 (PDT) X-Gm-Message-State: ALoCoQnsHoKcjOAkbFkImK7/Hduun8G99bJmOnzN+fjiz1Zl8d7qUuDMeODlbpAYadpyzZMkJGri X-Received: by 10.52.22.110 with SMTP id c14mr277001vdf.28.1381754938774; Mon, 14 Oct 2013 05:48:58 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp221006vcz; Mon, 14 Oct 2013 05:48:58 -0700 (PDT) X-Received: by 10.15.61.73 with SMTP id h49mr3256539eex.57.1381754933816; Mon, 14 Oct 2013 05:48:53 -0700 (PDT) Received: from eu1sys200aog121.obsmtp.com (eu1sys200aog121.obsmtp.com [207.126.144.151]) by mx.google.com with SMTP id e49si52632102eep.261.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Oct 2013 05:48:53 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.151 is neither permitted nor denied by best guess record for domain of maxime.coquelin@st.com) client-ip=207.126.144.151; Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob121.postini.com ([207.126.147.11]) with SMTP ID DSNKUlvoDrvx8mC1xThPF1xJ4+asZvs9mIn+@postini.com; Mon, 14 Oct 2013 12:48:53 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D780DBF; Mon, 14 Oct 2013 12:46:37 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1D9885064; Mon, 14 Oct 2013 12:33:50 +0000 (GMT) Received: from lmenx29l.lme.st.com (lmenx29l.lme.st.com [10.201.23.80] (may be forged)) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BOS40145 (AUTH lme00137); Mon, 14 Oct 2013 14:47:00 +0200 From: Maxime COQUELIN To: Wolfram Sang , srinivas.kandagatla@st.com, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Grant Likely , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Cc: stephen.gallimore@st.com, stuart.menefy@st.com, Lee Jones , gabriel.fernandez@st.com, Maxime Coquelin Subject: [PATCH v5 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC Date: Mon, 14 Oct 2013 14:46:51 +0200 Message-Id: <1381754813-4679-4-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381754813-4679-1-git-send-email-maxime.coquelin@st.com> References: <1381754813-4679-1-git-send-email-maxime.coquelin@st.com> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch supplies I2C configuration to STiH415 SoC. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..a85fbf1 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; };