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[86.14.224.72]) by mx.google.com with ESMTPSA id f7sm6549731wjb.7.2014.01.11.05.05.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 11 Jan 2014 05:05:56 -0800 (PST) From: Leif Lindholm To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-efi@vger.kernel.org, matt.fleming@intel.com, roy.franz@linaro.org, msalter@redhat.com, linux@arm.linux.org.uk, grant.likely@secretlab.ca, patches@linaro.org, Leif Lindholm Subject: [PATCH v4 2/5] arm: add new asm macro update_sctlr Date: Sat, 11 Jan 2014 13:05:21 +0000 Message-Id: <1389445524-30623-3-git-send-email-leif.lindholm@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1389445524-30623-1-git-send-email-leif.lindholm@linaro.org> References: <1389445524-30623-1-git-send-email-leif.lindholm@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: leif.lindholm@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.41 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , A new macro for setting/clearing bits in the SCTLR. Signed-off-by: Leif Lindholm Suggested-by: Will Deacon --- arch/arm/include/asm/assembler.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5c22851..aba6458 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -383,4 +383,17 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #endif .endm +#ifdef CONFIG_CPU_CP15 +/* Macro for setting/clearing bits in sctlr */ + .macro update_sctlr, set:req, clear:req, tmp:req, tmp2:req + mrc p15, 0, \tmp, c1, c0, 0 + ldr \tmp2, =\set + orr \tmp, \tmp, \tmp2 + ldr \tmp2, =\clear + mvn \tmp2, \tmp2 + and \tmp, \tmp, \tmp2 + mcr p15, 0, \tmp, c1, c0, 0 + .endm +#endif + #endif /* __ASM_ASSEMBLER_H__ */