From patchwork Thu May 22 16:47:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 30642 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f72.google.com (mail-oa0-f72.google.com [209.85.219.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9188B20671 for ; Thu, 22 May 2014 16:51:48 +0000 (UTC) Received: by mail-oa0-f72.google.com with SMTP id l6sf17179810oag.11 for ; Thu, 22 May 2014 09:51:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=6zWTlFOysjgI/pNVMBbT3wnlVnPgrxcZrWmNLfqmVlI=; b=GUTZREl59WdRS9iXf9m96K/Qd382GCa7Lku13gOI0XeZO1AFO93BFFkeTpy2KymDay tkKnMAO7SUaKli0XoaJQ5/qJKmGP7fxwZzX6NSRdikwoyna/T31j9uhcDR1MUZeanx5U 2O+AtoX650PGJvD+rvhq6lHxJ9d5Vc0tKiS0lP1cxoq93z18E6tUmE5jthv7UnEMLjoG qSLySYpNuFZHO+zJgZTMW5D6XWgDga5aC7NH+M+ZjWOuvC+qGi5OC777n935QIw15/VG JdfgklacEc8fw+EddLBHSG2KSFOU5zdgawKgyhMAYcioqCySMmYusNyuzLmcS285vxAq dekQ== X-Gm-Message-State: ALoCoQlNFmhq+yH8M0pab9xCPYjEVWYfDIGRkw4fKEMuIWr120kplKsQm0N5TvLBdzg2r22aTsWw X-Received: by 10.42.203.202 with SMTP id fj10mr24170502icb.0.1400777508195; Thu, 22 May 2014 09:51:48 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.98.52 with SMTP id n49ls1449991qge.29.gmail; Thu, 22 May 2014 09:51:48 -0700 (PDT) X-Received: by 10.58.74.201 with SMTP id w9mr1554400vev.56.1400777508066; Thu, 22 May 2014 09:51:48 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id rn6si200880vcb.80.2014.05.22.09.51.48 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 09:51:48 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id id10so1402124vcb.20 for ; Thu, 22 May 2014 09:51:48 -0700 (PDT) X-Received: by 10.58.66.195 with SMTP id h3mr1580618vet.57.1400777507961; Thu, 22 May 2014 09:51:47 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp215303vcb; Thu, 22 May 2014 09:51:47 -0700 (PDT) X-Received: by 10.68.218.231 with SMTP id pj7mr68773362pbc.95.1400777506828; Thu, 22 May 2014 09:51:46 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id xe4si485030pab.28.2014.05.22.09.51.46 for ; Thu, 22 May 2014 09:51:46 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753236AbaEVQvg (ORCPT + 27 others); Thu, 22 May 2014 12:51:36 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:48897 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752983AbaEVQs1 (ORCPT ); Thu, 22 May 2014 12:48:27 -0400 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.25]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s4MGlbwo028208; Thu, 22 May 2014 17:47:37 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 4E34E1AE3433; Thu, 22 May 2014 17:47:35 +0100 (BST) From: Will Deacon To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, monstr@monstr.eu, dhowells@redhat.com, broonie@linaro.org, benh@kernel.crashing.org, peterz@infradead.org, paulmck@linux.vnet.ibm.com, Will Deacon Subject: [PATCH v2 18/18] asm-generic: io: define relaxed accessor macros unconditionally Date: Thu, 22 May 2014 17:47:30 +0100 Message-Id: <1400777250-17335-19-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1400777250-17335-1-git-send-email-will.deacon@arm.com> References: <1400777250-17335-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.deacon@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Now that no architectures using asm-generic/io.h define their own relaxed accessors, the dummy definitions can be used unconditionally. Cc: Arnd Bergmann Signed-off-by: Will Deacon --- include/asm-generic/io.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 9ccedeb06522..f5611abb82ed 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -53,27 +53,21 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) #endif #define readb __raw_readb -#ifndef readb_relaxed #define readb_relaxed readb -#endif #define readw readw static inline u16 readw(const volatile void __iomem *addr) { return __le16_to_cpu(__raw_readw(addr)); } -#ifndef readw_relaxed #define readw_relaxed readw -#endif #define readl readl static inline u32 readl(const volatile void __iomem *addr) { return __le32_to_cpu(__raw_readl(addr)); } -#ifndef readl_relaxed #define readl_relaxed readl -#endif #ifndef __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem *addr) @@ -97,19 +91,13 @@ static inline void __raw_writel(u32 b, volatile void __iomem *addr) #endif #define writeb __raw_writeb -#ifndef writeb_relaxed #define writeb_relaxed writeb -#endif #define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) -#ifndef writew_relaxed #define writew_relaxed writew -#endif #define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) -#ifndef writel_relaxed #define writel_relaxed writel -#endif #ifdef CONFIG_64BIT #ifndef __raw_readq @@ -124,9 +112,7 @@ static inline u64 readq(const volatile void __iomem *addr) { return __le64_to_cpu(__raw_readq(addr)); } -#ifndef readq_relaxed #define readq_relaxed readq -#endif #ifndef __raw_writeq static inline void __raw_writeq(u64 b, volatile void __iomem *addr) @@ -136,9 +122,7 @@ static inline void __raw_writeq(u64 b, volatile void __iomem *addr) #endif #define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr) -#ifndef writeq_relaxed #define writeq_relaxed writeq -#endif #endif /* CONFIG_64BIT */ #ifndef PCI_IOBASE