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[209.132.180.67]) by mx.google.com with ESMTP id vr10si16844033pbc.102.2015.09.09.23.06.49; Wed, 09 Sep 2015 23:06:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753132AbbIJGGm (ORCPT + 28 others); Thu, 10 Sep 2015 02:06:42 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:56944 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751294AbbIJGGg (ORCPT ); Thu, 10 Sep 2015 02:06:36 -0400 Received: from 172.24.1.47 (EHLO szxeml427-hub.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CSC43742; Thu, 10 Sep 2015 14:06:27 +0800 (CST) Received: from u105-115.huawei.com (10.141.105.115) by szxeml427-hub.china.huawei.com (10.82.67.182) with Microsoft SMTP Server id 14.3.235.1; Thu, 10 Sep 2015 14:06:15 +0800 From: Chen Feng To: , , CC: , , , , Subject: [PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Date: Thu, 10 Sep 2015 14:06:13 +0800 Message-ID: <1441865173-104103-3-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441865173-104103-1-git-send-email-puck.chen@hisilicon.com> References: <1441865173-104103-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.141.105.115] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: puck.chen@hisilicon.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add reset driver for hi6220-hikey board,this driver supply deassert of IP. on hi6220 SoC. Signed-off-by: Chen Feng --- drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/hisilicon/Kconfig | 5 +++ drivers/reset/hisilicon/Makefile | 1 + drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+) create mode 100644 drivers/reset/hisilicon/Kconfig create mode 100644 drivers/reset/hisilicon/Makefile create mode 100644 drivers/reset/hisilicon/hi6220_reset.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0615f50..df37212 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER If unsure, say no. source "drivers/reset/sti/Kconfig" +source "drivers/reset/hisilicon/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..331d7b2 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_HISI) += hisilicon/ diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig new file mode 100644 index 0000000..bceed14 --- /dev/null +++ b/drivers/reset/hisilicon/Kconfig @@ -0,0 +1,5 @@ +config COMMON_RESET_HI6220 + tristate "Hi6220 Clock Driver" + depends on (ARCH_HISI && RESET_CONTROLLER) + help + Build the Hisilicon Hi6220 reset driver. diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile new file mode 100644 index 0000000..c932f86 --- /dev/null +++ b/drivers/reset/hisilicon/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c new file mode 100644 index 0000000..a88fc57 --- /dev/null +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -0,0 +1,74 @@ +/* + * Hisilicon Hi6220 reset controller driver + * + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Feng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void __iomem *src_base; +static DEFINE_SPINLOCK(reset_lock); + +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + unsigned long timeout; + unsigned long flags; + int bit; + u32 val; + + int bank = idx >> 8; + int offset = idx & 0xff; + + spin_lock_irqsave(&reset_lock, flags); + + val = readl(src_base + (bank * 0x10)); + writel(val | BIT(offset), src_base + (bank * 0x10)); + + spin_unlock_irqrestore(&reset_lock, flags); + + return 0; + +} + +static struct reset_control_ops hi6220_reset_ops = { + .deassert = hi6220_reset_module, +}; + +static struct reset_controller_dev hi6220_reset_dev = { + .ops = &hi6220_reset_ops, + .nr_resets = 0xffff, +}; + +static void __init hi6220_reset_init(void) +{ + struct device_node *np; + struct reset_control *test = NULL; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); + if (!np) { + pr_err("find reset node in dts error!\n"); + return; + } + src_base = of_iomap(np, 0); + WARN_ON(!src_base); + + hi6220_reset_dev.of_node = np; + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + reset_controller_register(&hi6220_reset_dev); +} + +postcore_initcall(hi6220_reset_init); +