From patchwork Tue Dec 1 09:14:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 57481 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp2041135lbb; Tue, 1 Dec 2015 01:18:09 -0800 (PST) X-Received: by 10.66.153.198 with SMTP id vi6mr98326787pab.37.1448961480560; Tue, 01 Dec 2015 01:18:00 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ug9si378944pac.225.2015.12.01.01.18.00; Tue, 01 Dec 2015 01:18:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756070AbbLAJR5 (ORCPT + 28 others); Tue, 1 Dec 2015 04:17:57 -0500 Received: from mail-wm0-f44.google.com ([74.125.82.44]:35930 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755930AbbLAJQE (ORCPT ); Tue, 1 Dec 2015 04:16:04 -0500 Received: by wmww144 with SMTP id w144so163916162wmw.1 for ; Tue, 01 Dec 2015 01:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YZFIm4Zl81XopatedcskBtal1uS0tkPSxmkWXBhWG5E=; b=m8MlEQF4wGkopkv+PcThrVj39GjbK0da7F5kYdOa+Q+lo5J6DP0COdq2bkA2PvEAAf IXu7/M9KJPmxLQUAwvvmqhMqZkz5wIcclC0UxXapo4dH6/AFE5zUh4r/IlXS6lp4e+TP rvKy6Norj80ax/vdPMb9+2MwJEURnvUXESQdejIgCHwxbDtnn9l/mSbiHWsc8PdP2Io6 ZhncH/sZMJksiWn6/zZzm6CejK7mOX2bZEmV25TtDgaTKc0qC4P+GmXOrUHK8pdnkxVW 6epEWHtSP4jtrxBUAt34b1yCvjDbg4IIUb7w3Pm7Cx/j2b588N0voiFDXHH+e4bVA9Yu +jQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YZFIm4Zl81XopatedcskBtal1uS0tkPSxmkWXBhWG5E=; b=E6oKa6eNOcpG1yUq5h8NDlbv7dx6F5/lKzzrGcmHaJ8QwE5fUu/qFgiIkD9vjYKSiG M1tjRaw7cL6+zBnL9C3obmser10QfaE6C6aVNNeeLmu+A5sKOVvq4X2xj+n7sHdQpbqH hgWs6YMF8kTnPqZTVDO1KMCBDfuWrlLwGT8rYLrjEApOkAmazsuMpfAuM/l+JgLAoPzO JajsfPLpqWZxdfyerQKxSLBRA5kyAm+k9qpD43+O6+KHsLtOg2blwY/fyP9stjPbnAH8 DDCy4vmGjuqOJUqMBn52iPqWn+OuvrXNGFSTn9YIUhPCRNg81Y7I7qeol4CFyodUwuap 5DBw== X-Gm-Message-State: ALoCoQlxK7FzkRQIveg3lgOvKTIxE29x+K7gO7TZ0Huve3FftRp6gn1/0RMcvXo4B4QDm1E8FLCZ X-Received: by 10.28.142.205 with SMTP id q196mr36085619wmd.42.1448961363523; Tue, 01 Dec 2015 01:16:03 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id t64sm25290428wmf.23.2015.12.01.01.16.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Dec 2015 01:16:03 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul Cc: Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Andy Gross , Archit Taneja , Stanimir Varbanov Subject: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised Date: Tue, 1 Dec 2015 11:14:57 +0200 Message-Id: <1448961299-15161-3-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> References: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we write BAM_IRQ_CLR register with zero even when no BAM_IRQ occured. This write has some bad side effects when the BAM instance is for the crypto engine. In case of crypto engine some of the BAM registers are xPU protected and they cannot be controlled by the driver. Signed-off-by: Stanimir Varbanov --- drivers/dma/qcom_bam_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index dc9da477eb69..0f06f3b7a72b 100644 --- a/drivers/dma/qcom_bam_dma.c +++ b/drivers/dma/qcom_bam_dma.c @@ -800,13 +800,17 @@ static irqreturn_t bam_dma_irq(int irq, void *data) if (srcs & P_IRQ) tasklet_schedule(&bdev->task); - if (srcs & BAM_IRQ) + if (srcs & BAM_IRQ) { clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); - /* don't allow reorder of the various accesses to the BAM registers */ - mb(); + /* + * don't allow reorder of the various accesses to the BAM + * registers + */ + mb(); - writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); + writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); + } return IRQ_HANDLED; }