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[209.132.180.67]) by mx.google.com with ESMTP id ah10si11609871pad.118.2016.01.14.13.47.39; Thu, 14 Jan 2016 13:47:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755125AbcANVra (ORCPT + 29 others); Thu, 14 Jan 2016 16:47:30 -0500 Received: from mail-pf0-f176.google.com ([209.85.192.176]:36668 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754998AbcANVrV (ORCPT ); Thu, 14 Jan 2016 16:47:21 -0500 Received: by mail-pf0-f176.google.com with SMTP id n128so106058309pfn.3 for ; Thu, 14 Jan 2016 13:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2/3OF+XUdXWPEk0UKYsGAIblPjEv9f4xoKJg0i+Ewhc=; b=gBHEHGBnNBe/CMSQySnc4h5gzSZq3XiM1XKWh30ILY/YFpVjJuk1XbAL3WFNJ6qRfd F1t8z7jI3tWXgWj9FfasOoq02C+HAYeltzg44FeONiAVhi+8jFikfbBugtsU98TDh0bw Dp7ZFm8KDvqmLcfW5dlZDO8SgqfxLWMAyqgE0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2/3OF+XUdXWPEk0UKYsGAIblPjEv9f4xoKJg0i+Ewhc=; b=Qr+BS0DrO/1aFWn/fBctXBxIr4WCWqGMI3XirmVJQ313J5rcAsvDjNogtGOqVqmsuv 1MRPDZejX0e5mIp+RguSOrMg5NQUqcLi5qYB3V0oBX0x1YDsC2Pq/ISdjvkay175tYKX IjfGRDSERRyK7+TSTHIVc7snl/ng1QvaIWTvV52N7NSz0VdWoWPKsw/RtI33YDpAsz1U 2bRBiJHSMXWYWJ97PXevN5aOCUkMcDdek24YylyT9aaNbWMMdtp7a/ciOoUwOXcX6GMx qI5oWCfemb3G3Pe+zbhaY2mFgrsBk0Y7YXdfOi9qRKejj7XB70PwPogUcOzehRS3UwlI KXFw== X-Gm-Message-State: ALoCoQmO3nOn6oGKQvIxLCIKnsuRhgBbuDD1cR4yfiywpHQX08XzgrE/VW8DiM9tYF6GnU9wPHCyvcEnIVqx1FUgtQbEpx9n+Q== X-Received: by 10.98.69.93 with SMTP id s90mr9551782pfa.77.1452808040063; Thu, 14 Jan 2016 13:47:20 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id c87sm11383309pfj.41.2016.01.14.13.47.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jan 2016 13:47:19 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, rabin@rab.in, Mathieu Poirier Subject: [PATCH V8 12/23] coresight: etm3x: implementing user/kernel mode tracing Date: Thu, 14 Jan 2016 14:46:06 -0700 Message-Id: <1452807977-8069-13-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> References: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 6 ++- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 4 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 63 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 3 ++ 4 files changed, 75 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 44585d4adb26..51597cb2c08a 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -110,7 +110,10 @@ #define ETM_MODE_STALL BIT(2) #define ETM_MODE_TIMESTAMP BIT(3) #define ETM_MODE_CTXID BIT(4) -#define ETM_MODE_ALL 0x1f +#define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \ + ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \ + ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \ + ETM_MODE_EXCL_USER) #define ETM_SQR_MASK 0x3 #define ETM_TRACEID_MASK 0x3f @@ -296,5 +299,6 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) extern const struct attribute_group *coresight_etm_groups[]; int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); +void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 387c79fd9d5e..cbb4046c1070 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -162,6 +162,10 @@ static ssize_t mode_store(struct device *dev, config->ctrl |= ETMCR_CTXID_SIZE; else config->ctrl &= ~ETMCR_CTXID_SIZE; + + if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) + etm_config_trace_mode(config); + spin_unlock(&drvdata->spinlock); return size; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index d0f2a55f9b16..c683b267ecfc 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -234,6 +234,69 @@ void etm_set_default(struct etm_config *config) config->ctxid_mask = 0x0; } +void etm_config_trace_mode(struct etm_config *config) +{ + u32 flags, mode; + + mode = config->mode; + + mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); + + /* excluding kernel AND user space doesn't make sense */ + if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) + return; + + /* nothing to do if neither flags are set */ + if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) + return; + + flags = (1 << 0 | /* instruction execute */ + 3 << 3 | /* ARM instruction */ + 0 << 5 | /* No data value comparison */ + 0 << 7 | /* No exact mach */ + 0 << 8); /* Ignore context ID */ + + /* No need to worry about single address comparators. */ + config->enable_ctrl2 = 0x0; + + /* Bit 0 is address range comparator 1 */ + config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; + + /* + * On ETMv3.5: + * ETMACTRn[13,11] == Non-secure state comparison control + * ETMACTRn[12,10] == Secure state comparison control + * + * b00 == Match in all modes in this state + * b01 == Do not match in any more in this state + * b10 == Match in all modes excepts user mode in this state + * b11 == Match only in user mode in this state + */ + + /* Tracing in secure mode is not supported at this time */ + flags |= (0 << 12 | 1 << 10); + + if (mode & ETM_MODE_EXCL_USER) { + /* exclude user, match all modes except user mode */ + flags |= (1 << 13 | 0 << 11); + } else { + /* exclude kernel, match only in user mode */ + flags |= (1 << 13 | 1 << 11); + } + + /* + * The ETMEEVR register is already set to "hard wire A". As such + * all there is to do is setup an address comparator that spans + * the entire address range and configure the state and mode bits. + */ + config->addr_val[0] = (u32) 0x0; + config->addr_val[1] = (u32) ~0x0; + config->addr_acctype[0] = flags; + config->addr_acctype[1] = flags; + config->addr_type[0] = ETM_ADDR_TYPE_RANGE; + config->addr_type[1] = ETM_ADDR_TYPE_RANGE; +} + static void etm_enable_hw(void *info) { int i; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index ed116b303e87..932f34a84d96 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -34,6 +34,9 @@ #define TIMEOUT_US 100 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define ETM_MODE_EXCL_KERN BIT(30) +#define ETM_MODE_EXCL_USER BIT(31) + enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS,