From patchwork Mon Feb 1 17:28:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 60945 Delivered-To: patch@linaro.org Received: by 10.112.130.2 with SMTP id oa2csp170000lbb; Mon, 1 Feb 2016 09:28:30 -0800 (PST) X-Received: by 10.66.218.40 with SMTP id pd8mr40328335pac.159.1454347710177; Mon, 01 Feb 2016 09:28:30 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s137si47433779pfs.11.2016.02.01.09.28.29; Mon, 01 Feb 2016 09:28:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754402AbcBAR20 (ORCPT + 30 others); Mon, 1 Feb 2016 12:28:26 -0500 Received: from mail-wm0-f52.google.com ([74.125.82.52]:32815 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754373AbcBAR2Z (ORCPT ); Mon, 1 Feb 2016 12:28:25 -0500 Received: by mail-wm0-f52.google.com with SMTP id l66so81069902wml.0 for ; Mon, 01 Feb 2016 09:28:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=atJuhL6gHKfHomBzj8fi8ZIpTaRJUcuYl0VAwfz0h84=; b=Z/df/J6ahiLB3XK+B2g7B5v02vl9kqn2RYg87aIqgcDuNLJD2kpS7d6Igduq3NqqJN V19X87x5a/AGM6xTL5YDo5sqz35Otx33drwcymPPoJ+0ELBO4Fuir0dy56E+RduFrwgF xLa832sHCD/GVOLfJnT+WA2kdZAldPcbkvGJc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=atJuhL6gHKfHomBzj8fi8ZIpTaRJUcuYl0VAwfz0h84=; b=VO4UQAPq6/jFHkwW2kgvwPL5ysJT0HWvYQHLanHPy6vd5j3nHaDQ7M0OTFT91OPQAA dpve9HTF3W04EO17jM0/uwIxB9RuJY0/HPDfarZxCurjEaAhyoHhHGYJZuKCYLzWALGa PnyHuRzL9deATfcoWKYLFeu5eLAdDOAfXJ9kZFI2EjxuwDRsKsHPny4TZtMvtSsnySfu TXLaXaThvH5xZ7q8TqnSgS3dN+axUd7ZmLju5OMr933DM6AOa5snNyPb1KAhDNwxBOr6 +/B/X/CBFU6BAJwg4XuGJjXJ9ziOrDlVwzeWidU+BRXGSTnR/HYeDFd34+jcOHmX/Aq8 bVkQ== X-Gm-Message-State: AG10YOTYI7qulxH8SAvWzPexPLfGGp0DYtkE5KyHP7vXnkjHJ9vEYhPRlVJkzhVyiPoQVvv/ X-Received: by 10.28.228.87 with SMTP id b84mr13924576wmh.36.1454347704116; Mon, 01 Feb 2016 09:28:24 -0800 (PST) Received: from localhost.localdomain (host-92-13-246-184.as43234.net. [92.13.246.184]) by smtp.gmail.com with ESMTPSA id ct2sm30104465wjb.46.2016.02.01.09.28.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Feb 2016 09:28:23 -0800 (PST) From: Srinivas Kandagatla To: Patrick Lai , alsa-devel@alsa-project.org Cc: Banajit Goswami , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 02/15] ASoC: qcom: add wrdma register details to lpass_variant Date: Mon, 1 Feb 2016 17:28:20 +0000 Message-Id: <1454347700-10404-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454347622-9970-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1454347622-9970-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds wrdma related register offsets and shifts into lpass variant structure. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/lpass.h | 3 +++ 1 file changed, 3 insertions(+) -- 1.9.1 diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index 0b63e2e..ab684a8 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -71,6 +71,9 @@ struct lpass_variant { u32 rdma_reg_base; u32 rdma_reg_stride; u32 rdma_channels; + u32 wrdma_reg_base; + u32 wrdma_reg_stride; + u32 wrdma_channels; /** * on SOCs like APQ8016 the channel control bits start