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[209.132.180.67]) by mx.google.com with ESMTP id aa6si48289583pad.148.2016.02.29.22.37.33; Mon, 29 Feb 2016 22:37:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752049AbcCAGhP (ORCPT + 30 others); Tue, 1 Mar 2016 01:37:15 -0500 Received: from mail-pf0-f179.google.com ([209.85.192.179]:33193 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751991AbcCAGhK (ORCPT ); Tue, 1 Mar 2016 01:37:10 -0500 Received: by mail-pf0-f179.google.com with SMTP id 124so45351539pfg.0 for ; Mon, 29 Feb 2016 22:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=YRezMspNWMD3Gr1pSqNlrck4cgzlG+ZrxpyLCg8Bw8Rz8FO0nxxuI8z1X6olErBEtB iQWTDOD62guvYTK2Nx/RmrHF4QjFbbV9GeRZWw4q0taj0oC7Wi7iu19QNjTheBoTofnY qBgd+7rrb4KCK7VIPtI7u4JMGMC6vzqiadSWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=M/4lyK1lj/UmENdRe+ijp+yqqk4zzBBAcHNxnT+yRQe2vvmv3prEC04WNoubfB2RVH m95cKzuyxCc1Q4/77fufk5qnU/qDI8ER4QhRudJECFle8atbViLJ+rPLo9RjWJTpScj4 RKlLLxsd+gqMB1TkRC+ItOCL5v/MCNkSN7FY1q+YQCEm8y2VSTM+wZPSXgPozFmwO6m9 WHtTpbJGqeGcMAoSHJL6+rF1kVvqmIeo3SL19VDwZ5r+W3mriB4urMpNQR68n1DNJeJw JTGvbGNakuJiY4Z2eUHoednHPIJmt+Ln/wLAYJ2pQvNIWCjxGcEg+8Kiub1KT2R3+Hjc 3xqA== X-Gm-Message-State: AD7BkJJi2TPyA3HzkaO3YzXm0H9TK2mRsvQZ6sKy7xBg7iKDg6mZOqGQVspp8kcs99OidrUp X-Received: by 10.98.9.27 with SMTP id e27mr28130029pfd.59.1456814229918; Mon, 29 Feb 2016 22:37:09 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id y21sm26485895pfa.85.2016.02.29.22.37.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Feb 2016 22:37:08 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: mike.leach@arm.com, Michael.Williams@arm.com, al.grant@arm.com, tor@ti.com, nicolas.guion@st.com, pratikp@codeaurora.org, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH V4 3/4] coresight-stm: Bindings for System Trace Macrocell Date: Tue, 1 Mar 2016 14:35:08 +0800 Message-Id: <1456814109-21311-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456814109-21311-1-git-send-email-zhang.chunyan@linaro.org> References: <1456814109-21311-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.