From patchwork Tue Mar 22 20:23:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 64206 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2295779lbc; Tue, 22 Mar 2016 13:26:02 -0700 (PDT) X-Received: by 10.66.253.68 with SMTP id zy4mr56790910pac.81.1458678362525; Tue, 22 Mar 2016 13:26:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fu10si18406666pad.117.2016.03.22.13.26.02; Tue, 22 Mar 2016 13:26:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752729AbcCVUZz (ORCPT + 29 others); Tue, 22 Mar 2016 16:25:55 -0400 Received: from mail-io0-f175.google.com ([209.85.223.175]:33782 "EHLO mail-io0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752235AbcCVUX7 (ORCPT ); Tue, 22 Mar 2016 16:23:59 -0400 Received: by mail-io0-f175.google.com with SMTP id c63so75971920iof.0 for ; Tue, 22 Mar 2016 13:23:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wHQ350uYbwXR2HN0aHjRhTE0mrDN22TyM41LzajCBu8=; b=j9acngi/ydiX/okzmFjRQvs82xKaqzsmyAlr9YfhHk7z7eOj6xri28pKXgJ3iHaxtG EUB0il5OijQ/ep1/Hj4H/ALf4i51XVmaCdDWmuUpjWgJquWjLOzM9KfI5YbpHjJQJE56 in6zlXOckI84FYDoqKTFVYs1E9Tz6hKNMq5RQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wHQ350uYbwXR2HN0aHjRhTE0mrDN22TyM41LzajCBu8=; b=SU01U+sTg2dyNChYDxaO6koPKuAayV2epC6L62dOWMoMax7/Gj7tNYVUPjUREfaE4K 49r+onhB632ZQja7dPPUMvxyOKLzDiYUhPHfeQwErh01bHLm4I+RqJ7DmjkaaUqk8/GG 4fk7NfY3UP4KhVGgktfe5JyRI2aIALC2z9qoaFjrlGPjVS3m9ObsWY9rKKsnE8m/t7CI 4AFkkqDOrRA+qa1K18jThxZUNqu70hWf4cirAZ84WVWkzkBWD2V3KlMPWa7wjbBlFMzt +rbOOJMshdwObTo87ywWnzXUr8WNO3E1ZmPF0PTg40ChOnnF6lrG84XTwSAik86MbGiV JuHg== X-Gm-Message-State: AD7BkJLKXxc6tLXNX4szIX6yR4E7ZzKV8pRx/j1BlEuJ6WOHrCIaJf1DyptYbU4LoalU/TB1 X-Received: by 10.107.2.69 with SMTP id 66mr42282568ioc.8.1458678238906; Tue, 22 Mar 2016 13:23:58 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xo2sm8092061igb.0.2016.03.22.13.23.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 13:23:57 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 11/14] coresight: tmc: keep track of memory width Date: Tue, 22 Mar 2016 14:23:19 -0600 Message-Id: <1458678202-3447-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> References: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 +++----- drivers/hwtracing/coresight/coresight-tmc.c | 1 + drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 3 files changed, 6 insertions(+), 5 deletions(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index c533b4494969..2cad1aa1949f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -42,18 +42,16 @@ void tmc_etb_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { - enum tmc_mem_intf_width memwidth; u8 memwords; char *bufp; u32 read_data; int i; - memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10); - if (memwidth == TMC_MEM_INTF_WIDTH_32BITS) + if (drvdata->memwidth == TMC_MEM_INTF_WIDTH_32BITS) memwords = 1; - else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS) + else if (drvdata->memwidth == TMC_MEM_INTF_WIDTH_64BITS) memwords = 2; - else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS) + else if (drvdata->memwidth == TMC_MEM_INTF_WIDTH_128BITS) memwords = 4; else memwords = 8; diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index c614fe160f8a..beeac81ff2fe 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -304,6 +304,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); + drvdata->memwidth = BMVAL(devid, 8, 10); if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { if (np) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 6dbd70861b17..a6fb7a9fec5a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -103,6 +103,7 @@ enum tmc_mem_intf_width { * @size: @buf size. * @mode: how this TMC is being used. * @config_type: TMC variant, must be of type @tmc_config_type. + * @memwidth: width of the memory interface databus, powers of two. * @trigger_cntr: amount of words to store after a trigger. */ struct tmc_drvdata { @@ -119,6 +120,7 @@ struct tmc_drvdata { u32 size; local_t mode; enum tmc_config_type config_type; + enum tmc_mem_intf_width memwidth; u32 trigger_cntr; };