From patchwork Mon Apr 11 08:38:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 65478 Delivered-To: patch@linaro.org Received: by 10.112.43.237 with SMTP id z13csp1338511lbl; Mon, 11 Apr 2016 01:40:25 -0700 (PDT) X-Received: by 10.66.157.129 with SMTP id wm1mr31542179pab.159.1460364020100; Mon, 11 Apr 2016 01:40:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id rk11si2552758pac.222.2016.04.11.01.40.19; Mon, 11 Apr 2016 01:40:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753603AbcDKIjn (ORCPT + 29 others); Mon, 11 Apr 2016 04:39:43 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:33461 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753436AbcDKIjc (ORCPT ); Mon, 11 Apr 2016 04:39:32 -0400 Received: by mail-wm0-f47.google.com with SMTP id f198so135445132wme.0 for ; Mon, 11 Apr 2016 01:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TIblPeNxgSRaD7ArU7HFrnaVaI9QvFYmOTEo6KLsdh8=; b=bJgNB2rR1D0g5y//BlsQx533RGSFySeyuwFXyLaAOVSJPlgANGgB3OR/KP0D1VH5kr 1BHCvpVaMqobNQlGguNSb9nfmqrlvR/4jgcqvtxjheEAec48j/CxM9OJVWOqg3QLDL5M n9ksGsARin/5NC2WmaFUacVvHoqtrdY4rXbUc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TIblPeNxgSRaD7ArU7HFrnaVaI9QvFYmOTEo6KLsdh8=; b=jvKSXbLRWLaPBk08BZgzAXbth/BMbqozzC/cziqA8DdiUsE104+YL4mHAwwcC3ha2b +DYoan4PUBmz/C0VrPM8MUvJSCHHpid9HXXyBYxSFsjXiX4D2mBfxgkps9G/xqIorQuL V84lJ1r8Nf+eNKzp4sMqOQ+8K1+TOtRv18O9G+M0ukGSYnuPlbbuOvMVzxTynsDEM3SB ojp1Y7U5baQNsxXTTp5NbF2Ly4NbB4uvrS0R/dxZE9PUfZRxz6mz9pTzd9BOiEBP+ovO avg9aN2m/0XRiedgTR1DwGjf/YfUcwXu6Luq383ALSyMnq5x5Y+yG4WsCMobWbUaFxi0 8Xfw== X-Gm-Message-State: AD7BkJK6qGgUBWaowuM70YFtVci5sh6/YShIeft0bmu/LHFVHEObJ8AkDpea4YgdhHr3UQKS X-Received: by 10.194.243.226 with SMTP id xb2mr22216866wjc.35.1460363971454; Mon, 11 Apr 2016 01:39:31 -0700 (PDT) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id d1sm16078604wmh.18.2016.04.11.01.39.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Apr 2016 01:39:31 -0700 (PDT) From: Stanimir Varbanov To: Rob Herring , Mark Rutland , Vinod Koul , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Archit Taneja , Sinan Kaya , Pramod Gurav , Stanimir Varbanov Subject: [PATCH v3 5/6] dmaengine: qcom: bam_dma: use correct pipe FIFO size Date: Mon, 11 Apr 2016 11:38:42 +0300 Message-Id: <1460363923-16296-6-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1460363923-16296-1-git-send-email-stanimir.varbanov@linaro.org> References: <1460363923-16296-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The pipe fifo size register must instruct the bam hw how many hw descriptors can be pushed to fifo. Currently we instruct the hw with 32KBytes but wrap the tail in bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This leads to stalled transactions when the tail wraps. Fix this by use the correct fifo size in BAM_P_FIFO_SIZES register i.e. 32K - 8. Signed-off-by: Stanimir Varbanov --- drivers/dma/qcom/bam_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.7.9.5 diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index d0f878a78fae..7e5ad1c25e21 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -459,7 +459,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan, */ writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); - writel_relaxed(BAM_DESC_FIFO_SIZE, + writel_relaxed(BAM_MAX_DATA_SIZE, bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */