From patchwork Fri Jun 17 15:14:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 70349 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp335346qgy; Fri, 17 Jun 2016 08:17:13 -0700 (PDT) X-Received: by 10.36.227.67 with SMTP id d64mr3823363ith.18.1466176623764; Fri, 17 Jun 2016 08:17:03 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p64si99558pfi.102.2016.06.17.08.17.03; Fri, 17 Jun 2016 08:17:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755666AbcFQPQ2 (ORCPT + 30 others); Fri, 17 Jun 2016 11:16:28 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:37080 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933665AbcFQPOq (ORCPT ); Fri, 17 Jun 2016 11:14:46 -0400 Received: by mail-wm0-f51.google.com with SMTP id a66so3947389wme.0 for ; Fri, 17 Jun 2016 08:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/FBI944tYsLvyZE6QJqdD/Sv4e0SwziV5nE48Dg6KL8=; b=iAlJo5YTIc6iMhs5l5qExYqMXRtJzvgy6m0pZrTFj1u5AVQGqgyxRPTH1HUFdEciDg 1K3vFzTTt8tThYhoDSJ60WX0enep4rhqV92RSgAPl6n/Lis/kqSkqmB2frp2xlfHXkxI RM2/suTxK2xzwLlbxTdZ+afm0sNsvI1zUc+ho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/FBI944tYsLvyZE6QJqdD/Sv4e0SwziV5nE48Dg6KL8=; b=MQkHr6RFVyMS1RsT8CyvamjeTL2+z1QFZUOqXszFknxlMuHWBSFtDAa1dv2OFeyjA9 nni7oO15IwNwrmDdV4ewpj82GwWfIkVk+tcXhkP8YXcuJrwX0qaykyCukk5QPGt8Ks8B nbftm0GRnWB9hWjppB3kfCB14W7YLXcuPrEqnurfDpzDbM0KRvWHPTouz63UVGr3haks 3UjuK8xZwPD+8BxjDdLYAF1p3PAUo6UPJeO2OUF3VCC20BSmDejT2IkahruLuOdvByrh TFwJVFPNBYbmG+J7wLuxAgk2z8PCTrb/V4RP/chXKyFXuJkGuMcxay1BVJRCmhqT198k UM4g== X-Gm-Message-State: ALyK8tL+O78d1V0xoisxDagaX8/6AJG3L6H0Rf2p0AT6NfYI6pXCwffTSlx5ElwxyrAT1EuQ X-Received: by 10.28.85.3 with SMTP id j3mr254529wmb.0.1466176480597; Fri, 17 Jun 2016 08:14:40 -0700 (PDT) Received: from localhost.localdomain (host-92-17-247-99.as13285.net. [92.17.247.99]) by smtp.gmail.com with ESMTPSA id o129sm4240934wmb.17.2016.06.17.08.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Jun 2016 08:14:39 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross Cc: Rob Herring , David Brown , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 11/16] arm64: dts: msm8996: add support to blsp1_spi0 pinctrl Date: Fri, 17 Jun 2016 16:14:08 +0100 Message-Id: <1466176454-28084-12-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds pinctrl nodes required for blsp1_spi0. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 79ed98c..9fd37a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -13,6 +13,40 @@ &msmgpio { + blsp1_spi0_default: blsp1_spi0_default { + pinmux { + function = "blsp_spi1"; + pins = "gpio0", "gpio1", "gpio3"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio2"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio2"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi0_sleep: blsp1_spi0_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + blsp1_i2c2_default: blsp1_i2c2_default { pinmux { function = "blsp_i2c3";