From patchwork Tue Oct 11 12:58:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 77485 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp337150qge; Tue, 11 Oct 2016 06:02:07 -0700 (PDT) X-Received: by 10.66.81.42 with SMTP id w10mr6835960pax.141.1476190926922; Tue, 11 Oct 2016 06:02:06 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id uh1si3371121pab.215.2016.10.11.06.02.02; Tue, 11 Oct 2016 06:02:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753014AbcJKNAL (ORCPT + 27 others); Tue, 11 Oct 2016 09:00:11 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48358 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751378AbcJKM6u (ORCPT ); Tue, 11 Oct 2016 08:58:50 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u9BCwkGF015459; Tue, 11 Oct 2016 07:58:46 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9BCwkOv024759; Tue, 11 Oct 2016 07:58:46 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Tue, 11 Oct 2016 07:58:46 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9BCweZ5014511; Tue, 11 Oct 2016 07:58:44 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring CC: , , , , , Subject: [PATCH 1/4] PCI: designware: Fix compiler warning Date: Tue, 11 Oct 2016 18:28:32 +0530 Message-ID: <1476190715-16884-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1476190715-16884-1-git-send-email-kishon@ti.com> References: <1476190715-16884-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix the following compilation warning in dw_pcie_readl_unroll() and dw_pcie_writel_unroll() by just invoking dw_pcie_readl_rc() and dw_pcie_writel_rc() respectively instead of adding redundant code. pcie-designware.c: In function 'dw_pcie_readl_unroll': pcie-designware.c:165:32: warning: passing argument 2 of 'pp->ops->readl_rc' makes integer from pointer without a cast [-Wint-conversion] return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg); ^ pcie-designware.c:165:32: note: expected 'u32 {aka unsigned int}' but argument is of type 'void *' pcie-designware.c: In function 'dw_pcie_writel_unroll': pcie-designware.c:176:31: warning: passing argument 3 of 'pp->ops->writel_rc' makes integer from pointer without a cast [-Wint-conversion] pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg); ^ drivers/pci/host/pcie-designware.c:176:31: note: expected 'u32 {aka unsigned int}' but argument is of type 'void *' Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/host/pcie-designware.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 5ee8772..b8feea4 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -161,10 +161,7 @@ static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg); - - return readl(pp->dbi_base + offset + reg); + return dw_pcie_readl_rc(pp, offset + reg); } static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, @@ -172,10 +169,7 @@ static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg); - else - writel(val, pp->dbi_base + offset + reg); + dw_pcie_writel_rc(pp, offset + reg, val); } static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,