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[209.132.180.67]) by mx.google.com with ESMTP id oz10si26275682pac.14.2016.10.17.09.24.29; Mon, 17 Oct 2016 09:24:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935099AbcJQQYU (ORCPT + 27 others); Mon, 17 Oct 2016 12:24:20 -0400 Received: from mail-lf0-f54.google.com ([209.85.215.54]:34365 "EHLO mail-lf0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932702AbcJQQYL (ORCPT ); Mon, 17 Oct 2016 12:24:11 -0400 Received: by mail-lf0-f54.google.com with SMTP id b81so292709264lfe.1 for ; Mon, 17 Oct 2016 09:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=x8mUBrlN1gAwJG7Yu9tm5EssZjKsRw8Z0f2LkqYGC1s=; b=I5Z9xVoflF4liBqgH36gEFlRZUPz9OaVsPlCeilLjux3R1cygfQgT0QnsUDrqSy+mC hICq+AY7aQo1Eu3WIXdOpJO3yZroZIS6d2V8n4MSNr7dS3okGR7GwuYUmc0/Dy/iqBso IT6J23+iUstxyemn9NXzkkIWMSB+YVWLsrmt4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=x8mUBrlN1gAwJG7Yu9tm5EssZjKsRw8Z0f2LkqYGC1s=; b=Zs4F7mIjYf3BDdoe+XDsljvuVEvS5haXkdQsC2GAzx7NCRd18qtjYo65LPGzB5/1I6 Vy9nQpxmK3t3IKGSwnQ35syBzVwkvcyQnmoSPr5EtPu0n6qrksxYQd3N6Dp51tSo0D3h XzNM2bGAqLu9SO00xLiZ7wJuequ0tmUAsYmcmjnEWWwZpaJp83Tk0NazbWnpL2GeiS53 X1dY/nTQrVfrahQoYOzkCK7h5cGtTZ2Ny7712TI2NkrCxYYi234QWg/pSkR+uL6EpExZ TkgVQzSsyIClicwJpatrlzyGIr1HNqf0KkCLq0PTLmRa9kEBBR8OKAW7VthVDbw9/JWV +nOw== X-Gm-Message-State: AA6/9RkCYD84VtuzTQwg0uxijpNu3QVj6AMfEqqogJ6+gHsETYq7HPV3rsYR8OawCBtGlTWj X-Received: by 10.28.147.6 with SMTP id v6mr8734290wmd.3.1476721449309; Mon, 17 Oct 2016 09:24:09 -0700 (PDT) Received: from localhost.localdomain ([105.137.38.75]) by smtp.gmail.com with ESMTPSA id hb5sm54137258wjc.5.2016.10.17.09.24.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Oct 2016 09:24:08 -0700 (PDT) From: Ard Biesheuvel To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, tiwai@suse.com, perex@perex.cz Cc: travis@sgi.com, Ard Biesheuvel Subject: [PATCH] ALSA: hda - allow 40 bit DMA mask for NVidia devices Date: Mon, 17 Oct 2016 17:23:59 +0100 Message-Id: <1476721439-29519-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 49d9e77e72cf ("ALSA: hda - Fix system panic when DMA > 40 bits for Nvidia audio controllers") simply disabled any DMA exceeding 32 bits for NVidia devices, even though they are capable of performing DMA up to 40 bits. On some architectures (such as arm64), system memory is not guaranteed to be 32-bit addressable by PCI devices, and so this change prevents NVidia devices from working on platforms such as AMD Seattle. Since the original commit already mentioned that up to 40 bits of DMA is supported, and given that the code has been updated in the meantime to support a 40 bit DMA mask on other devices, revert commit 49d9e77e72cf and explicitly set the DMA mask to 40 bits for NVidia devices. Signed-off-by: Ard Biesheuvel --- sound/pci/hda/hda_intel.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index c3469f756ec2..c64d986009a9 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -341,8 +341,7 @@ enum { /* quirks for Nvidia */ #define AZX_DCAPS_PRESET_NVIDIA \ - (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ - AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ + (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ AZX_DCAPS_SNOOP_TYPE(NVIDIA)) #define AZX_DCAPS_PRESET_CTHDA \ @@ -1716,6 +1715,10 @@ static int azx_first_init(struct azx *chip) } } + /* NVidia hardware normally only supports up to 40 bits of DMA */ + if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) + dma_bits = 40; + /* disable 64bit DMA address on some devices */ if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { dev_dbg(card->dev, "Disabling 64bit DMA\n");