From patchwork Thu Oct 20 01:15:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 78371 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp533773qge; Wed, 19 Oct 2016 18:14:20 -0700 (PDT) X-Received: by 10.99.245.69 with SMTP id e5mr13460992pgk.92.1476926060286; Wed, 19 Oct 2016 18:14:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f5si39385149pgj.106.2016.10.19.18.14.19; Wed, 19 Oct 2016 18:14:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756690AbcJTBOD (ORCPT + 27 others); Wed, 19 Oct 2016 21:14:03 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:28334 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756296AbcJTBN7 (ORCPT ); Wed, 19 Oct 2016 21:13:59 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id u9K1D0se008597; Thu, 20 Oct 2016 10:13:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com u9K1D0se008597 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476925981; bh=B9f4JTEY7e6S8GFbQ1AMKfd4PByl/prrAQXuZVz7TDc=; h=From:To:Cc:Subject:Date:From; b=cAn5gE4eQKfHuEW6XVEayvkTWLz/wSxRSaap5DWK2vEzAX9KT05stUe8zU9MDWkoj hzUnlPCVssjXHRl9qMmDJjqwOtxDcm0XOijnOnkvBxq81kX4keEcbIQm8V+jSJ3x5x dulcjI1FfoWevRXsKZe5SSgqFHM2Xx8YQWhXwpi7XduPJgEL7Y+pVjwIP9G/ngvHTI 6KnZfzM/YdFop8/tzCqFrK5UKBoLATHEv2eoC2RXiNNi7eOpbL1H2Tia/Zvwt/3m0/ c1O/IBTq5kDQKgONuW61kOaX8xh8Ij8aFf8XWYufR6qHglrHJy3lCADdwl7a9ZNabG 5Xq1zHtGBfF1w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH v2 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Date: Thu, 20 Oct 2016 10:15:25 +0900 Message-Id: <1476926126-6079-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada --- Changes in v2: - Match the node name to the opp-hz property. arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 73e0acf..bb05f0a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -70,14 +70,18 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; }; @@ -86,6 +90,40 @@ method = "smc"; }; + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@245000000 { + opp-hz = /bits/ 64 <245000000>; + clock-latency-ns = <300>; + }; + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@490000000 { + opp-hz = /bits/ 64 <490000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@653334000 { + opp-hz = /bits/ 64 <653334000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@980000000 { + opp-hz = /bits/ 64 <980000000>; + clock-latency-ns = <300>; + }; + }; + clocks { refclk: ref { compatible = "fixed-clock";