From patchwork Mon Oct 24 08:00:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 78872 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp2440376qge; Mon, 24 Oct 2016 01:00:10 -0700 (PDT) X-Received: by 10.98.204.67 with SMTP id a64mr26192567pfg.120.1477296010739; Mon, 24 Oct 2016 01:00:10 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id iw1si11826766pac.148.2016.10.24.01.00.09; Mon, 24 Oct 2016 01:00:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935250AbcJXIAE (ORCPT + 27 others); Mon, 24 Oct 2016 04:00:04 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:26541 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933824AbcJXH71 (ORCPT ); Mon, 24 Oct 2016 03:59:27 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id u9O7w6Ho008639; Mon, 24 Oct 2016 16:58:09 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com u9O7w6Ho008639 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477295889; bh=H8j7BoUgwc6Kqw/5/0viK3H0rqEeyfgLv1EXQcnHZd0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2tD9cRqx4nzPu7ANbhQu+1nRTQ555eDq74hCcEZKnNPtwlpIBCBz3U1fKyw8ZDTyC /0hI8pEFAUd6O8YzrMmLekgXc70babXgqSk+N2qgqW91Uyz0hnZfBto5ZnordYF4O6 kI0aSapir6T3ClHDqIkwKimkBg8u0v7yvHFk5mqda7Os+pptorY8pQz5BKvQAJjyi8 VvN6OG+gTo7XlPlxwLBdXCJH/m5oXCkv/h9Swmo0C36XzxL3SCsCZ8ZjXpDhbjlsPk e0Rno9HjiJQfCew3KYoHz93Xu3jK6Sp+O/S3Rq1Ap19vT28NB++jQybGXVRosIJMlh wgF2y+OMXnHxA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-serial@vger.kernel.org Cc: Denys Vlasenko , Masahiro Yamada , Jiri Slaby , linux-kernel@vger.kernel.org, Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] serial: 8250_uniphier: hardcode regshift to avoid unneeded memory read Date: Mon, 24 Oct 2016 17:00:29 +0900 Message-Id: <1477296030-7517-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477296030-7517-1-git-send-email-yamada.masahiro@socionext.com> References: <1477296030-7517-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For this driver, uart_port::regshift is always 2. Hardcode the shift value instead of reading ->regshift to get an already known value. (pointed out by Denys Vlasenko) Furthermore, I am using register macros that are already shifted, which will save code a bit. Signed-off-by: Masahiro Yamada --- drivers/tty/serial/8250/8250_uniphier.c | 42 +++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 18 deletions(-) -- 1.9.1 diff --git a/drivers/tty/serial/8250/8250_uniphier.c b/drivers/tty/serial/8250/8250_uniphier.c index 417d9e7..92e7bb7 100644 --- a/drivers/tty/serial/8250/8250_uniphier.c +++ b/drivers/tty/serial/8250/8250_uniphier.c @@ -24,10 +24,22 @@ /* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */ #define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64 -#define UNIPHIER_UART_CHAR_FCR 3 /* Character / FIFO Control Register */ -#define UNIPHIER_UART_LCR_MCR 4 /* Line/Modem Control Register */ -#define UNIPHIER_UART_LCR_SHIFT 8 -#define UNIPHIER_UART_DLR 9 /* Divisor Latch Register */ +/* + * This hardware is similar to 8250, but its register map is a bit different: + * - MMIO32 (regshift = 2) + * - FCR is not at 2, but 3 + * - LCR and MCR are not at 3 and 4, they share 4 + * - Divisor latch at 9, no divisor latch access bit + */ + +#define UNIPHIER_UART_REGSHIFT 2 + +/* bit[15:8] = CHAR (not used), bit[7:0] = FCR */ +#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT)) +/* bit[15:8] = LCR, bit[7:0] = MCR */ +#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT)) +/* Divisor Latch Register */ +#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) struct uniphier8250_priv { int line; @@ -44,7 +56,7 @@ static int __init uniphier_early_console_setup(struct earlycon_device *device, /* This hardware always expects MMIO32 register interface. */ device->port.iotype = UPIO_MEM32; - device->port.regshift = 2; + device->port.regshift = UNIPHIER_UART_REGSHIFT; /* * Do not touch the divisor register in early_serial8250_setup(); @@ -68,17 +80,16 @@ static unsigned int uniphier_serial_in(struct uart_port *p, int offset) switch (offset) { case UART_LCR: - valshift = UNIPHIER_UART_LCR_SHIFT; + valshift = 8; /* fall through */ case UART_MCR: offset = UNIPHIER_UART_LCR_MCR; break; default: + offset <<= UNIPHIER_UART_REGSHIFT; break; } - offset <<= p->regshift; - /* * The return value must be masked with 0xff because LCR and MCR reside * in the same register that must be accessed by 32-bit write/read. @@ -97,7 +108,7 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value) offset = UNIPHIER_UART_CHAR_FCR; break; case UART_LCR: - valshift = UNIPHIER_UART_LCR_SHIFT; + valshift = 8; /* Divisor latch access bit does not exist. */ value &= ~UART_LCR_DLAB; /* fall through */ @@ -106,11 +117,10 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value) break; default: normal = true; + offset <<= UNIPHIER_UART_REGSHIFT; break; } - offset <<= p->regshift; - if (normal) { writel(value, p->membase + offset); } else { @@ -139,16 +149,12 @@ static void uniphier_serial_out(struct uart_port *p, int offset, int value) */ static int uniphier_serial_dl_read(struct uart_8250_port *up) { - int offset = UNIPHIER_UART_DLR << up->port.regshift; - - return readl(up->port.membase + offset); + return readl(up->port.membase + UNIPHIER_UART_DLR); } static void uniphier_serial_dl_write(struct uart_8250_port *up, int value) { - int offset = UNIPHIER_UART_DLR << up->port.regshift; - - writel(value, up->port.membase + offset); + writel(value, up->port.membase + UNIPHIER_UART_DLR); } static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port, @@ -234,7 +240,7 @@ static int uniphier_uart_probe(struct platform_device *pdev) up.port.type = PORT_16550A; up.port.iotype = UPIO_MEM32; - up.port.regshift = 2; + up.port.regshift = UNIPHIER_UART_REGSHIFT; up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE; up.capabilities = UART_CAP_FIFO;