From patchwork Wed Oct 26 17:31:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 79470 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp185129qge; Wed, 26 Oct 2016 10:32:55 -0700 (PDT) X-Received: by 10.98.192.135 with SMTP id g7mr6198705pfk.58.1477503175503; Wed, 26 Oct 2016 10:32:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d10si3190390pab.95.2016.10.26.10.32.54; Wed, 26 Oct 2016 10:32:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755978AbcJZRcu (ORCPT + 27 others); Wed, 26 Oct 2016 13:32:50 -0400 Received: from conuserg-11.nifty.com ([210.131.2.78]:53252 "EHLO conuserg-11.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754280AbcJZRcs (ORCPT ); Wed, 26 Oct 2016 13:32:48 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-11.nifty.com with ESMTP id u9QHVfpQ014504; Thu, 27 Oct 2016 02:31:44 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u9QHVfpQ014504 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477503104; bh=BY+DyAgjK+kRlSz0OJ2DV4MjO43rJb1Y+tG6aH7P6qU=; h=From:To:Cc:Subject:Date:From; b=S6bdlTeaQcz5aRF4F6cbFpLsZT5gNGOG2TUqn9fvkaCs4Vc7/W5UodagM7BEQr1ts Ydfff45R+8ODbqY2NapeFlYOe4YdWi0aUgOZ1zfjIJXYmCLRevJeaAtcR0JpNzeEvW GaM/f7M+xlTuC2ntQ4AeKfiMMY2oUQUaYfkgmdj9PvOZartCVSj7ufRIFJjHJF9Haa xdH7LilYNMSnPd04uc/y38SICVZD6+RLfi5cALou2ra+9x5X+eoahHzB9YmRB+lM5q sWVzpaXeaAEjQbZNIj1Owj4gTD5a0/njHDC1TaWKspJsMZikc8bnlkyLeZK4I5/VzG ilqSw0QU621jw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-clk@vger.kernel.org Cc: Masahiro Yamada , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] clk: uniphier: add CPU-gear change (cpufreq) support Date: Thu, 27 Oct 2016 02:31:27 +0900 Message-Id: <1477503088-26508-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Core support code for CPU frequency changes, which will be used by the generic cpufreq driver. The register view is different from the generic clk-mux; it has a separate status register, and an update bit to load the register setting. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/Makefile | 3 + drivers/clk/uniphier/clk-uniphier-core.c | 3 + drivers/clk/uniphier/clk-uniphier-cpugear.c | 115 ++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 17 +++- 4 files changed, 136 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/uniphier/clk-uniphier-cpugear.c -- 1.9.1 diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index f27b3603..665d1d6 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,8 +1,11 @@ obj-y += clk-uniphier-core.o + +obj-y += clk-uniphier-cpugear.o obj-y += clk-uniphier-fixed-factor.o obj-y += clk-uniphier-fixed-rate.o obj-y += clk-uniphier-gate.o obj-y += clk-uniphier-mux.o + obj-y += clk-uniphier-sys.o obj-y += clk-uniphier-mio.o obj-y += clk-uniphier-peri.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 26c53f7..0007218 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -27,6 +27,9 @@ static struct clk_hw *uniphier_clk_register(struct device *dev, const struct uniphier_clk_data *data) { switch (data->type) { + case UNIPHIER_CLK_TYPE_CPUGEAR: + return uniphier_clk_register_cpugear(dev, regmap, data->name, + &data->data.cpugear); case UNIPHIER_CLK_TYPE_FIXED_FACTOR: return uniphier_clk_register_fixed_factor(dev, data->name, &data->data.factor); diff --git a/drivers/clk/uniphier/clk-uniphier-cpugear.c b/drivers/clk/uniphier/clk-uniphier-cpugear.c new file mode 100644 index 0000000..9bff26e --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-cpugear.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "clk-uniphier.h" + +#define UNIPHIER_CLK_CPUGEAR_STAT 0 /* status */ +#define UNIPHIER_CLK_CPUGEAR_SET 4 /* set */ +#define UNIPHIER_CLK_CPUGEAR_UPD 8 /* update */ +#define UNIPHIER_CLK_CPUGEAR_UPD_BIT BIT(0) + +struct uniphier_clk_cpugear { + struct clk_hw hw; + struct regmap *regmap; + unsigned int regbase; + unsigned int mask; +}; + +#define to_uniphier_clk_cpugear(_hw) \ + container_of(_hw, struct uniphier_clk_cpugear, hw) + +static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index) +{ + struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw); + int ret; + unsigned int val; + + ret = regmap_write_bits(gear->regmap, + gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, + gear->mask, index); + if (ret) + return ret; + + ret = regmap_write_bits(gear->regmap, + gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, + UNIPHIER_CLK_CPUGEAR_UPD_BIT, + UNIPHIER_CLK_CPUGEAR_UPD_BIT); + if (ret) + return ret; + + return regmap_read_poll_timeout(gear->regmap, + gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, + val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT), + 0, 1); +} + +static u8 uniphier_clk_cpugear_get_parent(struct clk_hw *hw) +{ + struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw); + int num_parents = clk_hw_get_num_parents(hw); + int ret; + unsigned int val; + + ret = regmap_read(gear->regmap, + gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val); + if (ret) + return ret; + + val &= gear->mask; + + return val < num_parents ? val : -EINVAL; +} + +static const struct clk_ops uniphier_clk_cpugear_ops = { + .determine_rate = __clk_mux_determine_rate, + .set_parent = uniphier_clk_cpugear_set_parent, + .get_parent = uniphier_clk_cpugear_get_parent, +}; + +struct clk_hw *uniphier_clk_register_cpugear(struct device *dev, + struct regmap *regmap, + const char *name, + const struct uniphier_clk_cpugear_data *data) +{ + struct uniphier_clk_cpugear *gear; + struct clk_init_data init; + int ret; + + gear = devm_kzalloc(dev, sizeof(*gear), GFP_KERNEL); + if (!gear) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &uniphier_clk_cpugear_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = data->parent_names; + init.num_parents = data->num_parents, + + gear->regmap = regmap; + gear->regbase = data->regbase; + gear->mask = data->mask; + gear->hw.init = &init; + + ret = devm_clk_hw_register(dev, &gear->hw); + if (ret) + return ERR_PTR(ret); + + return &gear->hw; +} diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 0244dba..9707b0f 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -20,15 +20,24 @@ struct device; struct regmap; -#define UNIPHIER_CLK_MUX_MAX_PARENTS 8 +#define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS 16 +#define UNIPHIER_CLK_MUX_MAX_PARENTS 8 enum uniphier_clk_type { + UNIPHIER_CLK_TYPE_CPUGEAR, UNIPHIER_CLK_TYPE_FIXED_FACTOR, UNIPHIER_CLK_TYPE_FIXED_RATE, UNIPHIER_CLK_TYPE_GATE, UNIPHIER_CLK_TYPE_MUX, }; +struct uniphier_clk_cpugear_data { + const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS]; + unsigned int num_parents; + unsigned int regbase; + unsigned int mask; +}; + struct uniphier_clk_fixed_factor_data { const char *parent_name; unsigned int mult; @@ -58,6 +67,7 @@ struct uniphier_clk_data { enum uniphier_clk_type type; int idx; union { + struct uniphier_clk_cpugear_data cpugear; struct uniphier_clk_fixed_factor_data factor; struct uniphier_clk_fixed_rate_data rate; struct uniphier_clk_gate_data gate; @@ -90,7 +100,10 @@ struct uniphier_clk_data { }, \ } - +struct clk_hw *uniphier_clk_register_cpugear(struct device *dev, + struct regmap *regmap, + const char *name, + const struct uniphier_clk_cpugear_data *data); struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev, const char *name, const struct uniphier_clk_fixed_factor_data *data);