From patchwork Tue Nov 15 13:13:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fu Wei Fu X-Patchwork-Id: 82334 Delivered-To: patch@linaro.org Received: by 10.182.1.168 with SMTP id 8csp1697567obn; Tue, 15 Nov 2016 05:15:51 -0800 (PST) X-Received: by 10.107.183.8 with SMTP id h8mr18792859iof.163.1479215751890; Tue, 15 Nov 2016 05:15:51 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fb11si22097490pac.234.2016.11.15.05.15.51; Tue, 15 Nov 2016 05:15:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935359AbcKONPn (ORCPT + 26 others); Tue, 15 Nov 2016 08:15:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:35330 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932987AbcKONPg (ORCPT ); Tue, 15 Nov 2016 08:15:36 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id ED89064D9B; Tue, 15 Nov 2016 13:15:34 +0000 (UTC) Received: from Rei-Ayanami.localdomain.com (ovpn-8-16.pek2.redhat.com [10.72.8.16]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAFDDxGR009274; Tue, 15 Nov 2016 08:15:22 -0500 From: fu.wei@linaro.org To: rjw@rjwysocki.net, lenb@kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, marc.zyngier@arm.com, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, sudeep.holla@arm.com, hanjun.guo@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linaro-acpi@lists.linaro.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, rruigrok@codeaurora.org, harba@codeaurora.org, cov@codeaurora.org, timur@codeaurora.org, graeme.gregory@linaro.org, al.stone@linaro.org, jcm@redhat.com, wei@redhat.com, arnd@arndb.de, catalin.marinas@arm.com, will.deacon@arm.com, Suravee.Suthikulpanit@amd.com, leo.duran@amd.com, wim@iguana.be, linux@roeck-us.net, linux-watchdog@vger.kernel.org, tn@semihalf.com, christoffer.dall@linaro.org, julien.grall@arm.com, Fu Wei Subject: [PATCH v15 06/13] clocksource/drivers/arm_arch_timer: separate out arch_timer_uses_ppi init code to prepare for GTDT. Date: Tue, 15 Nov 2016 21:13:28 +0800 Message-Id: <1479215615-26950-7-git-send-email-fu.wei@linaro.org> In-Reply-To: <1479215615-26950-1-git-send-email-fu.wei@linaro.org> References: <1479215615-26950-1-git-send-email-fu.wei@linaro.org> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 15 Nov 2016 13:15:35 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fu Wei The patch refactor original arch_timer_uses_ppi init code: (1) Extract a subfunction: arch_timer_uses_ppi_init (2) Use the new subfunction in arch_timer_of_init and arch_timer_acpi_init Signed-off-by: Fu Wei --- drivers/clocksource/arm_arch_timer.c | 73 +++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 31 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 6de164f..af22953 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -821,40 +821,42 @@ static int __init arch_timer_common_init(void) return arch_timer_arch_init(); } -static int __init arch_timer_init(void) +/* + * If HYP mode is available, we know that the physical timer + * has been configured to be accessible from PL1. Use it, so + * that a guest can use the virtual timer instead. + * + * If no interrupt provided for virtual timer, we'll have to + * stick to the physical timer. It'd better be accessible... + * On ARM64, we we only use ARCH_TIMER_PHYS_NONSECURE_PPI in Linux. + * + * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE + * accesses to CNTP_*_EL1 registers are silently redirected to + * their CNTHP_*_EL2 counterparts, and use a different PPI + * number. + */ +static int __init arch_timer_uses_ppi_init(void) { - int ret; - /* - * If HYP mode is available, we know that the physical timer - * has been configured to be accessible from PL1. Use it, so - * that a guest can use the virtual timer instead. - * - * If no interrupt provided for virtual timer, we'll have to - * stick to the physical timer. It'd better be accessible... - * - * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE - * accesses to CNTP_*_EL1 registers are silently redirected to - * their CNTHP_*_EL2 counterparts, and use a different PPI - * number. - */ - if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) { - bool has_ppi; - - if (is_kernel_in_hyp_mode()) { - arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI; - has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI]; - } else { + if (is_hyp_mode_available() && is_kernel_in_hyp_mode()) { + arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI; + } else if (!arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) { + if (IS_ENABLED(CONFIG_ARM64)) + arch_timer_uses_ppi = ARCH_TIMER_PHYS_NONSECURE_PPI; + else arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; - has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] || - !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); - } - - if (!has_ppi) { - pr_warn("No interrupt available, giving up\n"); - return -EINVAL; - } } + if (arch_timer_ppi[arch_timer_uses_ppi]) + return 0; + + pr_warn("No interrupt available, giving up\n"); + return -EINVAL; +} + +static int __init arch_timer_init(void) +{ + int ret; + ret = arch_timer_register(); if (ret) return ret; @@ -870,7 +872,7 @@ static int __init arch_timer_init(void) static int __init arch_timer_of_init(struct device_node *np) { - int i; + int i, ret; if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { pr_warn("multiple nodes in dt, skipping\n"); @@ -902,6 +904,10 @@ static int __init arch_timer_of_init(struct device_node *np) of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; + ret = arch_timer_uses_ppi_init(); + if (ret) + return ret; + return arch_timer_init(); } CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); @@ -1011,6 +1017,7 @@ static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) /* Initialize per-processor generic timer */ static int __init arch_timer_acpi_init(struct acpi_table_header *table) { + int ret; struct acpi_table_gtdt *gtdt; if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { @@ -1041,6 +1048,10 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) /* Get the frequency from CNTFRQ */ arch_timer_detect_rate(NULL, NULL); + ret = arch_timer_uses_ppi_init(); + if (ret) + return ret; + /* Always-on capability */ arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);