From patchwork Sat Nov 26 18:06:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 84275 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp541830qgi; Sat, 26 Nov 2016 10:09:32 -0800 (PST) X-Received: by 10.99.101.65 with SMTP id z62mr25458316pgb.74.1480183772247; Sat, 26 Nov 2016 10:09:32 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q28si49451652pfl.44.2016.11.26.10.09.31; Sat, 26 Nov 2016 10:09:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753437AbcKZSJP (ORCPT + 25 others); Sat, 26 Nov 2016 13:09:15 -0500 Received: from conuserg-11.nifty.com ([210.131.2.78]:48015 "EHLO conuserg-11.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753150AbcKZSIP (ORCPT ); Sat, 26 Nov 2016 13:08:15 -0500 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-11.nifty.com with ESMTP id uAQI6Uer018512; Sun, 27 Nov 2016 03:06:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com uAQI6Uer018512 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1480183610; bh=NCVPmqoIvu0TjUJ9ZMW+oda8bNFD0kvC6dgZUU7yLh0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tY2mRjXqI/pbMBPxSwVmpI+lsFc2BoygwLzt6aqfTDlrSchFVIHRrGSZLYKie1SEF sIANRYqT+LV33wkKotiko/2tem/rbHyAI0K/VZH7h68L9qiQMxqU5c9v66/dD16zq2 h/DbiL500W2bEx5btC8FdEXgtyscePraWOKSVHO8Sp2IHX3wbG+S0sukbdHWZyPW4H 0gDxB15E+Ciev0DI/dau57/r4qccAWDavj3k0EG8rIe+rrsYKvnmw2tHISMig+Ne/1 ULfK5nci/eMaW8hjOuEN04i4x+Jd3fXtg8NM4JJw2o5tcnITnbNL8qTtSXbX380D+G gIR8oR1y5r4Gg== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse , Cyrille Pitchen Subject: [PATCH 21/39] mtd: nand: denali: support 64bit capable DMA engine Date: Sun, 27 Nov 2016 03:06:07 +0900 Message-Id: <1480183585-592-22-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480183585-592-1-git-send-email-yamada.masahiro@socionext.com> References: <1480183585-592-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current driver only supports the DMA engine up to 32 bit physical address, but there also exists 64 bit capable DMA engine for this IP. The data DMA setup sequence is completely different, so I added the 64 bit DMA code as a new function denali_setup_dma64(). The 32 bit one has been renamed to denali_setup_dma32(). Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 39 +++++++++++++++++++++++++++++++++++---- drivers/mtd/nand/denali.h | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ae44c01..752ad98 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -995,8 +995,30 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en) ioread32(denali->flash_reg + DMA_ENABLE); } -/* setups the HW to perform the data DMA */ -static void denali_setup_dma(struct denali_nand_info *denali, int op) +static void denali_setup_dma64(struct denali_nand_info *denali, int op) +{ + u32 mode; + const int page_count = 1; + u64 addr = denali->buf.dma_buf; + + mode = MODE_10 | BANK(denali->flash_bank) | denali->page; + + /* DMA is a three step process */ + + /* + * 1. setup transfer type, interrupt when complete, + * burst len = 64 bytes, the number of pages + */ + index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); + + /* 2. set memory low address */ + index_addr(denali, mode, addr); + + /* 3. set memory high address */ + index_addr(denali, mode, addr >> 32); +} + +static void denali_setup_dma32(struct denali_nand_info *denali, int op) { u32 mode; const int page_count = 1; @@ -1019,6 +1041,14 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op) index_addr(denali, mode | 0x14000, 0x2400); } +static void denali_setup_dma(struct denali_nand_info *denali, int op) +{ + if (denali->caps & DENALI_CAPS_DMA_64BIT) + denali_setup_dma64(denali, op); + else + denali_setup_dma32(denali, op); +} + /* * writes a page. user specifies type, and this function handles the * configuration details. @@ -1495,8 +1525,9 @@ int denali_init(struct denali_nand_info *denali) goto failed_req_irq; } - /* Is 32-bit DMA supported? */ - ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask(denali->dev, + DMA_BIT_MASK(denali->caps & DENALI_CAPS_DMA_64BIT ? + 64 : 32)); if (ret) { dev_err(denali->dev, "no usable DMA configuration\n"); goto failed_req_irq; diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index beadc8a..9bdf037 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -435,6 +435,7 @@ struct denali_nand_info { u32 max_banks; unsigned int caps; #define DENALI_CAPS_HW_ECC_FIXUP BIT(0) +#define DENALI_CAPS_DMA_64BIT BIT(1) }; extern int denali_init(struct denali_nand_info *denali);