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[209.132.180.67]) by mx.google.com with ESMTP id f12si48250378pgn.136.2016.12.01.01.10.46; Thu, 01 Dec 2016 01:10:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759432AbcLAJKW (ORCPT + 25 others); Thu, 1 Dec 2016 04:10:22 -0500 Received: from mail-wj0-f172.google.com ([209.85.210.172]:35912 "EHLO mail-wj0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757754AbcLAJEn (ORCPT ); Thu, 1 Dec 2016 04:04:43 -0500 Received: by mail-wj0-f172.google.com with SMTP id qp4so198462294wjc.3 for ; Thu, 01 Dec 2016 01:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5MsYshYlFXqQQkTa0qSeCOm6AwIDqfRXpJXusoOw/GQ=; b=T1wwpJdzUfhU5fZviQhQa98BN0WY/IAlI4CWQFu2+kouRFw/fwMHiSOAEle8zTYxdk 7nNu7SAFZghGfkH9wSHt/QBSgO9V+y/JCc1EZxX94LtjaSJRuEm1JhN1+cgxiLcAjdJI 7/C5kFnkTRjZ70eQ24w7A3aCNWF5oCF79a494= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5MsYshYlFXqQQkTa0qSeCOm6AwIDqfRXpJXusoOw/GQ=; b=S2n99dYwYi/EJZrS/mu9HdZuNFZeSMkIlXvn+KT/LY7fOTOlwHoXWdkG4Nt62x3BmT NKmsHCIqNV8kQ1fv/yeZpxRe+2HdCD4azloE2zYHfOoJiJL9YWQNx1pbRqt1xWcLT5U1 MPt8dCGHQG6t3m3PRPmn1ayyyhfv0pFRM8VQ4xI3qrADCdQHc2ZwO9zLzDlrgWJKllxc WBF7EEzXnVjJM1nELhBBGZYVav7DE6Ue2RS/tt62NFB1DGYW42DmygAK89L9S1Edfr+O 4YBAlrjWHV+ybap2yA4EyT9UQ6a4MwCNxDoVFiztLg4foUcEKYqzTfXp5ejB1CcHI0At 1hjg== X-Gm-Message-State: AKaTC01hF/5DpP2f6LcppsSIA1yhsKTdZ8bIpsioxYhxAeVGAZhwV8hYXiDkX4OX+SdNat5q X-Received: by 10.194.2.110 with SMTP id 14mr31175239wjt.206.1480583045580; Thu, 01 Dec 2016 01:04:05 -0800 (PST) Received: from mms-0440.wifi.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id w8sm12001881wmw.4.2016.12.01.01.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 01:04:05 -0800 (PST) From: Stanimir Varbanov To: Mauro Carvalho Chehab , Hans Verkuil Cc: Andy Gross , Bjorn Andersson , Stephen Boyd , Srinivas Kandagatla , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stanimir Varbanov , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v4 2/9] doc: DT: venus: binding document for Qualcomm video driver Date: Thu, 1 Dec 2016 11:03:14 +0200 Message-Id: <1480583001-32236-3-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480583001-32236-1-git-send-email-stanimir.varbanov@linaro.org> References: <1480583001-32236-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding document for Venus video encoder/decoder driver Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Stanimir Varbanov --- Rob, I have removed vmem clocks, interrupts and reg properties for vmem thing. Probably I will come with a separate platform driver fro that and pass the video memory DT node as phandle. .../devicetree/bindings/media/qcom,venus.txt | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,venus.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/media/qcom,venus.txt b/Documentation/devicetree/bindings/media/qcom,venus.txt new file mode 100644 index 000000000000..a64b4ea1ebba --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,venus.txt @@ -0,0 +1,82 @@ +* Qualcomm Venus video encode/decode accelerator + +- compatible: + Usage: required + Value type: + Definition: Value should contain one of: + - "qcom,msm8916-venus" + - "qcom,msm8996-venus" +- reg: + Usage: required + Value type: + Definition: Register ranges as listed in the reg-names property. +- reg-names: + Usage: required + Value type: + Definition: Should contain following entries: + - "base" Venus register base +- interrupts: + Usage: required + Value type: + Definition: Should contain interrupts as listed in the interrupt-names + property. +- interrupt-names: + Usage: required + Value type: + Definition: Should contain following entries: + - "venus" Venus interrupt line +- clocks: + Usage: required + Value type: + Definition: A List of phandle and clock specifier pairs as listed + in clock-names property. +- clock-names: + Usage: required + Value type: + Definition: Should contain the following entries: + - "core" Core video accelerator clock + - "iface" Video accelerator AHB clock + - "bus" Video accelerator AXI clock +- clock-names: + Usage: required for msm8996 + Value type: + Definition: Should contain the following entries: + - "subcore0" Subcore0 video accelerator clock + - "subcore1" Subcore1 video accelerator clock + - "mmssnoc_axi" Multimedia subsystem NOC AXI clock + - "mmss_mmagic_iface" Multimedia subsystem MMAGIC AHB clock + - "mmss_mmagic_mbus" Multimedia subsystem MMAGIC MAXI clock + - "mmagic_video_bus" MMAGIC video AXI clock + - "video_mbus" Video MAXI clock +- power-domains: + Usage: required + Value type: + Definition: A phandle and power domain specifier pairs to the + power domain which is responsible for collapsing + and restoring power to the peripheral. +- rproc: + Usage: required + Value type: + Definition: A phandle to remote processor responsible for + firmware loading and processor booting. + +- iommus: + Usage: required + Value type: + Definition: A list of phandle and IOMMU specifier pairs. + +* An Example + video-codec@1d00000 { + compatible = "qcom,msm8916-venus"; + reg = <0x01d00000 0xff000>; + reg-names = "base"; + interrupts = ; + interrupt-names = "venus"; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + power-domains = <&gcc VENUS_GDSC>; + rproc = <&venus_rproc>; + iommus = <&apps_iommu 5>; + };