From patchwork Wed Jan 4 19:32:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 89901 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp8642066qgi; Wed, 4 Jan 2017 11:35:44 -0800 (PST) X-Received: by 10.99.242.5 with SMTP id v5mr125256653pgh.181.1483558544043; Wed, 04 Jan 2017 11:35:44 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b69si73444944pli.91.2017.01.04.11.35.41; Wed, 04 Jan 2017 11:35:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031772AbdADTdt (ORCPT + 25 others); Wed, 4 Jan 2017 14:33:49 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:48777 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759557AbdADTd0 (ORCPT ); Wed, 4 Jan 2017 14:33:26 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v04JWJTZ004458; Wed, 4 Jan 2017 13:32:19 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v04JWJ2r030051; Wed, 4 Jan 2017 13:32:19 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 4 Jan 2017 13:32:18 -0600 Received: from ula0868495.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v04JWIYu009842; Wed, 4 Jan 2017 13:32:18 -0600 From: Murali Karicheri To: , , , , Subject: [PATCH] PCI: designware: fix asynchronous external abort in keystone PCIe h/w Date: Wed, 4 Jan 2017 14:32:30 -0500 Message-ID: <1483558350-8169-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Recent fixes for iATU unroll support introduced a bug that causes asynchronous external abort in Keystone PCIe h/w which doesn't have ATU port and the corresponding register. So the check should be moved below where dw_pcie_prog_outbound_atu() is called to avoid that being called on keystine PCIe h/w. Here is the backtrace [ 0.771174] OF: PCI: MEM 0x60000000..0x6fffffff -> 0x60000000 [ 0.778118] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 [ 0.785548] pgd = c0003000 [ 0.788347] [00000000] *pgd=80000800004003, *pmd=00000000 [ 0.793864] Internal error: : 1211 [#1] PREEMPT SMP ARM [ 0.799197] Modules linked in: [ 0.802351] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7 [ 0.810130] Hardware name: Keystone [ 0.813717] task: eb878000 task.stack: eb866000 [ 0.818356] PC is at dw_pcie_setup_rc+0x24/0x380 [ 0.823083] LR is at ks_pcie_host_init+0x10/0x170 Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host") Signed-off-by: Murali Karicheri Tested-by: Kishon Vijay Abraham I --- - Applies to pci/master - Bug was introduced in v4.9 - Tested on K2E EVM with SATA and DRA7-EVM with an intel PCI ethernet card drivers/pci/host/pcie-designware.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 1.9.1 Acked-By: Joao Pinto diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index bed1999..af8f6e9 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; - /* get iATU unroll support */ - pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); - dev_dbg(pp->dev, "iATU unroll: %s\n", - pp->iatu_unroll_enabled ? "enabled" : "disabled"); - /* set the number of lanes */ val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; @@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { + /* get iATU unroll support */ + pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); + dev_dbg(pp->dev, "iATU unroll: %s\n", + pp->iatu_unroll_enabled ? "enabled" : "disabled"); + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size);