From patchwork Mon Jan 16 10:40:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 91551 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1358604qgi; Mon, 16 Jan 2017 02:41:21 -0800 (PST) X-Received: by 10.98.89.195 with SMTP id k64mr8860995pfj.126.1484563281060; Mon, 16 Jan 2017 02:41:21 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p126si10580187pfg.209.2017.01.16.02.41.20; Mon, 16 Jan 2017 02:41:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751619AbdAPKlJ (ORCPT + 25 others); Mon, 16 Jan 2017 05:41:09 -0500 Received: from foss.arm.com ([217.140.101.70]:49464 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751517AbdAPKlD (ORCPT ); Mon, 16 Jan 2017 05:41:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A834707; Mon, 16 Jan 2017 02:41:03 -0800 (PST) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 009F43F220; Mon, 16 Jan 2017 02:41:01 -0800 (PST) From: Sudeep Holla To: linux-arm-kernel@lists.infradead.org Cc: Sudeep Holla , Rob Herring , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tan Xiaojun , Mark Rutland Subject: [PATCH v3 2/2] arm64: cacheinfo: add support to override cache levels via device tree Date: Mon, 16 Jan 2017 10:40:44 +0000 Message-Id: <1484563244-14743-2-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484563244-14743-1-git-send-email-sudeep.holla@arm.com> References: <1484563244-14743-1-git-send-email-sudeep.holla@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cache hierarchy can be identified through Cache Level ID(CLIDR) architected system register. However in some cases it will provide only the number of cache levels that are integrated into the processor itself. In other words, it can't provide any information about the caches that are external and/or transparent. Some platforms require to export the information about all such external caches to the userspace applications via the sysfs interface. This patch adds support to override the cache levels using device tree to take such external non-architected caches into account. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Tested-by: Tan Xiaojun Signed-off-by: Sudeep Holla --- arch/arm64/kernel/cacheinfo.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 9617301f76b5..3f2250fc391b 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -84,7 +84,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves; + unsigned int ctype, level, leaves, of_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -97,6 +97,17 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } + of_level = of_find_last_cache_level(cpu); + if (level < of_level) { + /* + * some external caches not specified in CLIDR_EL1 + * the information may be available in the device tree + * only unified external caches are considered here + */ + leaves += (of_level - level); + level = of_level; + } + this_cpu_ci->num_levels = level; this_cpu_ci->num_leaves = leaves; return 0;