From patchwork Fri Jan 20 11:22:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 92056 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp730658qgi; Fri, 20 Jan 2017 03:22:42 -0800 (PST) X-Received: by 10.84.213.9 with SMTP id f9mr20905181pli.138.1484911362129; Fri, 20 Jan 2017 03:22:42 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d74si6552000pfd.278.2017.01.20.03.22.41; Fri, 20 Jan 2017 03:22:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752116AbdATLWc (ORCPT + 25 others); Fri, 20 Jan 2017 06:22:32 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:37316 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752059AbdATLW2 (ORCPT ); Fri, 20 Jan 2017 06:22:28 -0500 Received: by mail-wm0-f51.google.com with SMTP id c206so38676361wme.0 for ; Fri, 20 Jan 2017 03:22:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R5PNJOuUNZ0TgS4mS+ALb4UY8CbowzkiyfRTK/S7H2U=; b=xmBOqpB6s/O1Z0JiUezENaSfWzA7rSozCz192I6ix7pxDyW+d8xwzgYKSZ6pFaVROC LaE2LiVvYs+1z0081Hi0iJNkB61lb9WZvsLhCPi5rqX02djBIduK2U3RMwQDd40oAuda Vg5j+OdgWNU1vU3VLmw04rvJZbX5pZtCeFiW7MhLNbXzoj0ye7krRSI9iS2n3uiuRWj/ Q55NLXSTBPyAeYmQ8YG1KC2+CC0fV+Ay/bOvggGWqug661QAo88i7FoF/99//3tREfOQ KTauZ2aLexjU97WHD+mWJdTNoZtRiVdqD1Vj7jYVS40WOLF9tt8ZHbxVjLLEnecglFWZ EItw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R5PNJOuUNZ0TgS4mS+ALb4UY8CbowzkiyfRTK/S7H2U=; b=M/wmcaSPGDImTEMs7M04cYiE16IuIxCqu/KW7ZuDLZ+97LZvtXizpd3oft9HZeXywE DQpsczJ1YDhDbq5gStT3T0NbhlgAq0qDZz4TmdehMujRGZEIqyycoZeMATvgtEwRYFuJ NF/L7+1/PZPNyu6+pmnm92d5v0bOSLZKfZK+i02JlKLL7/QYQeQkIt2+nFybSF1gtc5X X2R+uCQsM8phUP2J5r3F+tgzSh3WPiXOhBX60e51FAX9Owably5NOZJxIuWxNabquohd abB/L+NucUJtJwuRdKgeEHeByVpDQxocWm8nAN2zIEsxlpsRSBzwh/3equIb2A/f0vbw HWuw== X-Gm-Message-State: AIkVDXKZdyLbshILmgUwU7ydLFwwG1YQscV2Ca+9+N4OjlzSHdbXQkUn/XGWSWD5ErIcVgb7 X-Received: by 10.28.153.10 with SMTP id b10mr2767777wme.103.1484911341672; Fri, 20 Jan 2017 03:22:21 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id l74sm5482402wmg.2.2017.01.20.03.22.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 03:22:20 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v5 11/14] sata: ahci-da850: un-hardcode the MPY bits Date: Fri, 20 Jan 2017 12:22:02 +0100 Message-Id: <1484911325-23425-12-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1484911325-23425-1-git-send-email-bgolaszewski@baylibre.com> References: <1484911325-23425-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All platforms using this driver now register the SATA refclk. Remove the hardcoded default value from the driver and instead read the rate of the external clock and calculate the required MPY value from it. Signed-off-by: Bartosz Golaszewski --- drivers/ata/ahci_da850.c | 91 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 15 deletions(-) -- 2.9.3 diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 0b2b1a4..9ed404d 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -29,17 +29,8 @@ #define SATA_PHY_TXSWING(x) ((x) << 19) #define SATA_PHY_ENPLL(x) ((x) << 31) -/* - * The multiplier needed for 1.5GHz PLL output. - * - * NOTE: This is currently hardcoded to be suitable for 100MHz crystal - * frequency (which is used by DA850 EVM board) and may need to be changed - * if you would like to use this driver on some other board. - */ -#define DA850_SATA_CLK_MULTIPLIER 7 - static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg, - void __iomem *ahci_base) + void __iomem *ahci_base, u32 mpy) { unsigned int val; @@ -48,13 +39,61 @@ static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg, val &= ~BIT(0); writel(val, pwrdn_reg); - val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) | - SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | - SATA_PHY_ENPLL(1); + val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) | + SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1); writel(val, ahci_base + SATA_P0PHYCR_REG); } +static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate) +{ + u32 pll_output = 1500000000, needed; + + /* + * We need to determine the value of the multiplier (MPY) bits. + * In order to include the 12.5 multiplier we need to first divide + * the refclk rate by ten. + * + * __div64_32() turned out to be unreliable, sometimes returning + * false results. + */ + WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10"); + needed = pll_output / (refclk_rate / 10); + + /* + * What we have now is (multiplier * 10). + * + * Let's determine the actual register value we need to write. + */ + + switch (needed) { + case 50: + return 0x1; + case 60: + return 0x2; + case 80: + return 0x4; + case 100: + return 0x5; + case 120: + return 0x6; + case 125: + return 0x7; + case 150: + return 0x8; + case 200: + return 0x9; + case 250: + return 0xa; + default: + /* + * We should have divided evenly - if not, return an invalid + * value. + */ + return 0; + } +} + static int ahci_da850_softreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { @@ -126,9 +165,10 @@ static int ahci_da850_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ahci_host_priv *hpriv; - struct resource *res; void __iomem *pwrdn_reg; + struct resource *res; struct clk *clk; + u32 mpy; int rc; hpriv = ahci_platform_get_resources(pdev); @@ -150,6 +190,27 @@ static int ahci_da850_probe(struct platform_device *pdev) hpriv->clks[0] = clk; } + /* + * The second clock used by ahci-da850 is the external REFCLK. If we + * didn't get it from ahci_platform_get_resources(), let's try to + * specify the con_id in clk_get(). + */ + if (!hpriv->clks[1]) { + clk = clk_get(dev, "refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "unable to obtain the reference clock"); + return -ENODEV; + } else { + hpriv->clks[1] = clk; + } + } + + mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1])); + if (mpy == 0) { + dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy); + return -EINVAL; + } + rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; @@ -162,7 +223,7 @@ static int ahci_da850_probe(struct platform_device *pdev) if (!pwrdn_reg) goto disable_resources; - da850_sata_init(dev, pwrdn_reg, hpriv->mmio); + da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy); rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info, &ahci_platform_sht);