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[209.132.180.67]) by mx.google.com with ESMTP id c10si9131764pfj.210.2017.02.12.22.13.08; Sun, 12 Feb 2017 22:13:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752200AbdBMGM6 (ORCPT + 25 others); Mon, 13 Feb 2017 01:12:58 -0500 Received: from mail-pf0-f172.google.com ([209.85.192.172]:33868 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751875AbdBMGMz (ORCPT ); Mon, 13 Feb 2017 01:12:55 -0500 Received: by mail-pf0-f172.google.com with SMTP id e4so24898588pfg.1 for ; Sun, 12 Feb 2017 22:12:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=La7Jn1SzKfRA+zQd/l0SzJFQVVFhUAUhivKTcLryurU=; b=i+5hu7AFrbhI7CMcUM8NQDDReHOABR210V86unqyf7dPiSVcHs8p2W+aWeZOaJiH2y Kmb2Z4k7ktAcvAvYUKPovG6EU0qBMT+5za0bnnAuvezrWX93tPZXfm0465x4T6HM4neG o3z9AhC9F0wXALNUUPNp5+pRNG2eo853+jvSY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=La7Jn1SzKfRA+zQd/l0SzJFQVVFhUAUhivKTcLryurU=; b=CQV1l2j4hMIKck0bDqzB2Z857hTDczFhQQ3vFjG0cbC7KHjNnpKYtgoLMYDOtWQ4/S QXrGxghzHipub0Vz+R2LZVjUcTLJm5v4WibqJTOPRODuG5ivhqcGEWK+lyH6cCUU9N9O iklL7oaZURI4aSwjtmUctffh6RnRioOjURnkxu1Kw7QWLZq7+3wihlYQqBkul8grRavu i2HNTqerankuHl+gw6Em2880b7uHytQMcv+oGdyFb9O65RDt90JCmq7dCk7l7pTkYU0o nzKzyuKjG76UELY+a5Syv/OtzhNwmlt1TbbFzDrnQWd6eauNtJaSNTjfXTpu2NV6Eatl hdmQ== X-Gm-Message-State: AMke39k7xAfHM1dZMTjiR8hVjoGDxcnNKXAHKs+OrgOHe4/NKRBUh4MUnMn6DxxuNSeJUf5q X-Received: by 10.98.134.2 with SMTP id x2mr24437841pfd.158.1486966364807; Sun, 12 Feb 2017 22:12:44 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id l25sm18141998pfb.24.2017.02.12.22.12.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 12 Feb 2017 22:12:43 -0800 (PST) From: Leo Yan To: Mathieu Poirier , Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Thompson Cc: Leo Yan Subject: [PATCH RFC 3/3] arm64: dts: register Hi6220's coresight debug module Date: Mon, 13 Feb 2017 14:11:38 +0800 Message-Id: <1486966298-16767-4-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> References: <1486966298-16767-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Bind coresight debug driver for Hi6220. Signed-off-by: Leo Yan --- .../boot/dts/hisilicon/hikey_6220_coresight.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi index 77c2aab..e14d75c 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey_6220_coresight.dtsi @@ -15,6 +15,79 @@ #size-cells = <2>; compatible = "arm,amba-bus"; ranges; + + debug@0,f6590000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + debug@1,f6592000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6592000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + debug@2,f6594000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6594000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + debug@3,f6596000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf6596000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + debug@4,f65d0000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf65d0000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + debug@5,f65d2000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf65d2000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + debug@6,f65d4000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf65d4000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + debug@7,f65d6000 { + compatible = "arm,coresight-debug","arm,primecell"; + reg = <0 0xf65d6000 0 0x1000>; + default_enable; + clocks = <&sys_ctrl HI6220_CS_ATB>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + etm@0,f659c000 { compatible = "arm,coresight-etm4x","arm,primecell"; reg = <0 0xf659c000 0 0x1000>;