From patchwork Thu Feb 16 13:29:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 94072 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2505366qgi; Thu, 16 Feb 2017 05:30:35 -0800 (PST) X-Received: by 10.98.81.6 with SMTP id f6mr2620316pfb.180.1487251835382; Thu, 16 Feb 2017 05:30:35 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c7si6939499pgn.352.2017.02.16.05.30.35; Thu, 16 Feb 2017 05:30:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755076AbdBPNaY (ORCPT + 25 others); Thu, 16 Feb 2017 08:30:24 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:17966 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754503AbdBPNaK (ORCPT ); Thu, 16 Feb 2017 08:30:10 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v1GDTht9022578; Thu, 16 Feb 2017 07:29:43 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1GDThtG023166; Thu, 16 Feb 2017 07:29:43 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Thu, 16 Feb 2017 07:29:43 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v1GDTMcn017556; Thu, 16 Feb 2017 07:29:34 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jingoo Han , , , , , , , CC: Joao Pinto , , Kishon Vijay Abraham I Subject: [PATCH 1/4] PCI: dwc: designware: Add new *ops* for cpu addr fixup Date: Thu, 16 Feb 2017 18:59:09 +0530 Message-ID: <1487251752-12478-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487251752-12478-1-git-send-email-kishon@ti.com> References: <1487251752-12478-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 3 +++ drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d..14ee7a3 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pp->ops->cpu_addr_fixup) + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b871..8f3dcb2 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie);