From patchwork Wed Mar 22 20:07:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95828 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413488qgd; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) X-Received: by 10.98.134.142 with SMTP id x136mr48866067pfd.64.1490213569115; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 63si2130331pfl.124.2017.03.22.13.12.48; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751773AbdCVUMq (ORCPT + 11 others); Wed, 22 Mar 2017 16:12:46 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25274 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751454AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8964029452; Thu, 23 Mar 2017 05:08:35 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8964029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213316; bh=9SLvobft3NRln3CJ75gdFVjmMYflLyfuuo0womwkTgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XnM+iuR8iKBjIoCEBjTpUZNHBNdbqTnJ9kr9R/YYTnmET6FQkf96KD4VTJgOkYGFL XlT4maPqLP8H8GWd4adGnP3DcpAyq5+637aueTD4YHYN1pZtUZ1VdSh/8097GU5aux JFFeHxq6W6i6akEjem6PUoWuCzsOrzLDeKZ9dcSWb5uiSUkM5uwnE4NbjuoVwQ2G3C L3DWP4OXxaeB7IUXt+Vl3HH5uW/u3xvgpuXykFT0HmOIjYA1bsfYhOdwPzufb5Gu/e uxaKp0jMG+n6/t/x+qMirE55CwePE58XOEFb+i1QLGBFjyMSU39CZbtQ61Ks0mcIkT gXjhWk2kr35jw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 14/53] mtd: nand: denali: support 64bit capable DMA engine Date: Thu, 23 Mar 2017 05:07:13 +0900 Message-Id: <1490213273-8571-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current driver only supports the DMA engine up to 32 bit physical address, but there also exists 64 bit capable DMA engine for this IP. The data DMA setup sequence is completely different, so I added the 64 bit DMA code as a new function denali_setup_dma64(). The 32 bit one has been renamed to denali_setup_dma32(). Signed-off-by: Masahiro Yamada --- Changes in v2: - Change the capability prefix DENALI_CAPS_ -> DENALI_CAP_ drivers/mtd/nand/denali.c | 39 +++++++++++++++++++++++++++++++++++---- drivers/mtd/nand/denali.h | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 91f0def..513292f 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -999,8 +999,30 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en) ioread32(denali->flash_reg + DMA_ENABLE); } -/* setups the HW to perform the data DMA */ -static void denali_setup_dma(struct denali_nand_info *denali, int op) +static void denali_setup_dma64(struct denali_nand_info *denali, int op) +{ + uint32_t mode; + const int page_count = 1; + uint64_t addr = denali->buf.dma_buf; + + mode = MODE_10 | BANK(denali->flash_bank) | denali->page; + + /* DMA is a three step process */ + + /* + * 1. setup transfer type, interrupt when complete, + * burst len = 64 bytes, the number of pages + */ + index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); + + /* 2. set memory low address */ + index_addr(denali, mode, addr); + + /* 3. set memory high address */ + index_addr(denali, mode, addr >> 32); +} + +static void denali_setup_dma32(struct denali_nand_info *denali, int op) { uint32_t mode; const int page_count = 1; @@ -1023,6 +1045,14 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op) index_addr(denali, mode | 0x14000, 0x2400); } +static void denali_setup_dma(struct denali_nand_info *denali, int op) +{ + if (denali->caps & DENALI_CAP_DMA_64BIT) + denali_setup_dma64(denali, op); + else + denali_setup_dma32(denali, op); +} + /* * writes a page. user specifies type, and this function handles the * configuration details. @@ -1492,8 +1522,9 @@ int denali_init(struct denali_nand_info *denali) goto failed_req_irq; } - /* Is 32-bit DMA supported? */ - ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask(denali->dev, + DMA_BIT_MASK(denali->caps & DENALI_CAP_DMA_64BIT ? + 64 : 32)); if (ret) { dev_err(denali->dev, "No usable DMA configuration\n"); goto failed_req_irq; diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index ed42b16..a8e8d68 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -353,6 +353,7 @@ struct denali_nand_info { int max_banks; unsigned int caps; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) +#define DENALI_CAP_DMA_64BIT BIT(1) }; extern int denali_init(struct denali_nand_info *denali);