From patchwork Tue Mar 28 08:40:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 96119 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1602431qgd; Tue, 28 Mar 2017 01:41:32 -0700 (PDT) X-Received: by 10.98.155.28 with SMTP id r28mr29377034pfd.212.1490690492414; Tue, 28 Mar 2017 01:41:32 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u184si3533806pgd.21.2017.03.28.01.41.32; Tue, 28 Mar 2017 01:41:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754781AbdC1Ilb (ORCPT + 19 others); Tue, 28 Mar 2017 04:41:31 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:61085 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754718AbdC1Il3 (ORCPT ); Tue, 28 Mar 2017 04:41:29 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v2S8eAqt004954; Tue, 28 Mar 2017 17:40:11 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v2S8eAqt004954 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490690411; bh=OfTf+BDofvfklTfj9lExsOdZ2LY0QRs+pFW2aXlxBoM=; h=From:To:Cc:Subject:Date:From; b=Rgz1o/NW1auF56DCDpW8iQDEbMmNotvCpa9fAgG6zbV2lQkYqBpRS3Xuhh75CG4u8 8k9XLadEXzdfcC0YVocJ/TcSQCDRERN7qBCxvawZjYc+dWta/rqNAYg7hQMjuOk+dl 1L9pSycbcp9/fz6AoeBrV0hN30sZvRWuCGZCyF2cMZijT/rE7CMrNf3lcYwZF6g1Pe NbIoR6leI+esNegVNR2+feJY5plB+Lss0U+ZYf/VZ/QD5TIqFfhCgfnrtmEKVuzbxu 37Gxc3EgkdeHt1aWtD8BKK3T+0tuHCWOXIkhQkj+thiz3HqzXJ4LcL8bL/YeN8df/g eGzmJZXxxySlQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Philipp Zabel Cc: Masahiro Yamada , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] reset: uniphier: add NAND and eMMC reset control Date: Tue, 28 Mar 2017 17:40:08 +0900 Message-Id: <1490690408-2616-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset lines for the Denali NAND controller on all UniPhier SoCs, for the Cadence eMMC controller on LD11/LD20 SoCs. Signed-off-by: Masahiro Yamada --- Philipp, Sorry for sending this in the last minute. If it is not too late, please apply this for 4.12-rc1. Thanks! drivers/reset/reset-uniphier.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.7.4 diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 7af60bc..c4ba898 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -50,6 +50,15 @@ struct uniphier_reset_data { } /* System reset data */ +#define UNIPHIER_SLD3_SYS_RESET_NAND(id) \ + UNIPHIER_RESETX((id), 0x2004, 2) + +#define UNIPHIER_LD11_SYS_RESET_NAND(id) \ + UNIPHIER_RESETX((id), 0x200c, 0) + +#define UNIPHIER_LD11_SYS_RESET_EMMC(id) \ + UNIPHIER_RESETX((id), 0x200c, 2) + #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ UNIPHIER_RESETX((id), 0x2000, 10) @@ -66,11 +75,13 @@ struct uniphier_reset_data { UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ UNIPHIER_RESET_END, }; static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -79,6 +90,7 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { }; static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), @@ -87,6 +99,7 @@ static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { }; static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { + UNIPHIER_SLD3_SYS_RESET_NAND(2), UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), @@ -101,11 +114,15 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { }; static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { + UNIPHIER_LD11_SYS_RESET_NAND(2), + UNIPHIER_LD11_SYS_RESET_EMMC(4), UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ UNIPHIER_RESET_END, }; static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { + UNIPHIER_LD11_SYS_RESET_NAND(2), + UNIPHIER_LD11_SYS_RESET_EMMC(4), UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */