From patchwork Thu Jun 1 11:03:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 100888 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp700131obc; Thu, 1 Jun 2017 04:05:21 -0700 (PDT) X-Received: by 10.99.123.77 with SMTP id k13mr601655pgn.32.1496315121567; Thu, 01 Jun 2017 04:05:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496315121; cv=none; d=google.com; s=arc-20160816; b=e6ALdEreu7O1wx6CZiTFW6JFtI3IayLXMW384lkeQXcjFUka8IXuIHYvLAFRwdQG7z ZrM8jzMaed0/TZEkA++5A9MBdOCPe7Iahpww38u8g7a7MDOBs6Tt/fVGz7MH4wvGnrd9 CchCzdKNDjWG/XcEZNvGdSj9nCNCsYWhHQxPjPiueClla8/pBh0Q/mI69oT0YwEQDGMY BqneaQNPBXeR2DyOxTFNNeLT/JwKM3BpX/mZtjylXnMMva16tssUB8BOMJfWZAYOiDOq dud7CGIIYdbkBCchgbawfbagz6XYUl4HLnlNCwFuiwA3F1FgzcqgYPs7Ef1tgkh6bFj4 Hhrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=M2EgRNgx5CHEjRO2ia9zKDzT+onAHEGnykewCN8s4oI=; b=modl1FdVuCP4fMtyJLdxc3E+38X2Va3Q6+t3DUrG05LVJOgtT5RSAusMCAIQ/jwxak enIe1mwMI9WuAU0lf0N5mxsoM+RbxZH1TPsgJDOv95yeRrksGPUlZkpwJ82GHwR9Na8g M/cOHZsBP3SCaDXp/VCvBxpaUoOO9okTDZNULyoBfjLEku/whIyFAqHA9UNiYzglu30E S+cvkJ5C+CunH9lW3AfMoGqRKFWLW1PbmHX6QIDFeu9MvwfLRMLlIO+pWgWXLD0whbBA M31LWaHwd+V5ZfE1IxWliKKUizkr8XrM5u/piyXOxk1+HlYiIy2/jyvC84Gh/1amhD0Y pWNw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 66si19647489pfo.368.2017.06.01.04.05.21; Thu, 01 Jun 2017 04:05:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752017AbdFALFC (ORCPT + 25 others); Thu, 1 Jun 2017 07:05:02 -0400 Received: from foss.arm.com ([217.140.101.70]:54508 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751587AbdFALFB (ORCPT ); Thu, 1 Jun 2017 07:05:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D00321596; Thu, 1 Jun 2017 04:04:50 -0700 (PDT) Received: from gby.kfn.arm.com (unknown [10.45.48.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F2BE43F578; Thu, 1 Jun 2017 04:04:48 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Joe Perches , Ofir Drang , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Subject: [PATCH v2 13/20] staging: ccree: move request_mgr to generic bitfield ops Date: Thu, 1 Jun 2017 14:03:03 +0300 Message-Id: <1496314993-30229-14-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1496314993-30229-1-git-send-email-gilad@benyossef.com> References: <1496314993-30229-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org request_mgr was using custom bit field macros. move over to standard kernel bitfield ops. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_regs.h | 5 +++++ drivers/staging/ccree/ssi_request_mgr.c | 25 +++++++++++++++---------- 2 files changed, 20 insertions(+), 10 deletions(-) -- 2.1.4 diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index e272da4..f9d5280 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -26,6 +26,11 @@ #include "cc_bitops.h" +#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) +#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) + /* Register Offset macro */ #define CC_REG_OFFSET(unit_name, reg_name) \ (DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET) diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 683140a..a420fb9 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -35,8 +35,6 @@ #define SSI_MAX_POLL_ITER 10 -#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) - struct ssi_request_mgr_handle { /* Request manager resources */ unsigned int hw_queue_size; /* HW capability */ @@ -497,6 +495,15 @@ static void proc_completions(struct ssi_drvdata *drvdata) } } +static inline u32 cc_axi_comp_count(void __iomem *cc_base) +{ + /* The CC_HAL_READ_REGISTER macro implictly requires and uses + * a base MMIO register address variable named cc_base. + */ + return FIELD_GET(AXIM_MON_COMP_VALUE, + CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); +} + /* Deferred service handler, run as interrupt-fired tasklet */ static void comp_handler(unsigned long devarg) { @@ -516,24 +523,22 @@ static void comp_handler(unsigned long devarg) CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed += + cc_axi_comp_count(cc_base); while (request_mgr_handle->axi_completed) { do { proc_completions(drvdata); - /* At this point (after proc_completions()), request_mgr_handle->axi_completed is always 0. - The following assignment was changed to = (previously was +=) to conform KW restrictions. */ - request_mgr_handle->axi_completed = CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed = + cc_axi_comp_count(cc_base); } while (request_mgr_handle->axi_completed > 0); /* To avoid the interrupt from firing as we unmask it, we clear it now */ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed += + cc_axi_comp_count(cc_base); } }