From patchwork Wed Jun 7 11:52:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103247 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1715778obh; Wed, 7 Jun 2017 04:58:20 -0700 (PDT) X-Received: by 10.98.21.17 with SMTP id 17mr30418347pfv.71.1496836700483; Wed, 07 Jun 2017 04:58:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496836700; cv=none; d=google.com; s=arc-20160816; b=prZXvdmulqKfWfzxITTSPpm/5U6aHG1Iwe9LjxM+QU0cMXzFneRr3coHWnqTcmRKzn 1V+3Jxn2MMjxbtSlfwKUndr6k/i+VZ2T/ZpN9p1S44TiE6V4RHkoTIImAa8U0rRZrxPH dq0v5dYnjIedAgz5ypDneSafGjjE4YmC8LyB9lZu4RMEuNCbCNE5AoJtAjptXaU354Ha V7dUiGc3Qn3t1IffzM98RiwwYCK7irljHcgTkFYkWeFRnvwoPQRuTPa+3t6BPYafg6cm q12XznPYxO4nYbP39tEoj/zGrBb2cAwYeiBkXSalAgSxRoki5A/rNbgwXx+nLrhelzdC 7ung== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=XkQ9MNDTKfnQZu+hwJXVy3XifPnRRCHQRc3IG+CSGYY=; b=wQf3iXyRWDZqUoTN2PRcO6BQXq4NtbIjTvndaixFHEB9L7z2WjO4XCcyxTfzj/dQpr OuRqrjgQ4KSKwcP1DhHMcNwSJYHt0fBdGJmg21/qn4S1QIQTLleFpJT6Bpp191lFKjPB EAIVKEj4w62MMjG3qctcSBvhgA/2cwDhA5/9LRHoVQpqVgomM/m/3BJZZreQSj0WYbxq Xj/MjdBFJ/hlTJ2nu6LwXOnYtqD63zR2RFp2cv1QJrwGO5KZUwQVhO2YybKU6Oy1Ibm4 5q29vjYpg1IMoEgrCc5SEguVMz0pUMlCEANQPlawm3z7BjiX9PkVmwpMMZMFaJv2gceB LpFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c41si636611plj.187.2017.06.07.04.58.20; Wed, 07 Jun 2017 04:58:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751798AbdFGL5t (ORCPT + 25 others); Wed, 7 Jun 2017 07:57:49 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:42632 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751617AbdFGLz2 (ORCPT ); Wed, 7 Jun 2017 07:55:28 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v57BqjZc014276; Wed, 7 Jun 2017 20:53:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v57BqjZc014276 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496836382; bh=XkQ9MNDTKfnQZu+hwJXVy3XifPnRRCHQRc3IG+CSGYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dDTYwUnp+eUNvS+NEI8npzBSWoeXnmTmQz1JLLefXcBK7HcLxweJ8kmier3S+ce8L jvxamYWmXprI41I0/qucjZh2TJlfVX4u3DmBI2E5U5MKsGg6yUaqWoCmONmMNqiTED I8wubQSCG7NkR5rMxFMItYoq1Pc0kGv1A3rQx+skrIlvIlKs2jcgVpaSvHTlqVIJoj ARE91bRnLyg0Ph8aqguoPXVo8EFJ5C6acxGhhayYfaTk/dBEmaTHTvwn9Dm5CTjC4J PICjhXq9e2huFeWqdanL5a2YFU2UasG7/ou/Ji2VYUAyHIMER5r8D+wfWn7Bjk795w 3vEr5rnEJWNIA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v5 13/23] mtd: nand: denali: switch over to cmd_ctrl instead of cmdfunc Date: Wed, 7 Jun 2017 20:52:22 +0900 Message-Id: <1496836352-8016-14-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> References: <1496836352-8016-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc(). This is needed for nand_onfi_set_features(). Besides, we see /* TODO: Read OOB data */ comment line. It would be possible to add more commands along with the current implementation, but having ->cmd_ctrl() seems a better approach from the discussion with Boris [1]. Rely on the default ->cmdfunc() from the framework and implement the driver's own ->cmd_ctrl(). Also add ->write_byte(), which is needed for write direction commands. [1] https://lkml.org/lkml/2017/3/15/97 Signed-off-by: Masahiro Yamada --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 104 +++++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 52 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index c3382954cf27..95bce6b341d7 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -230,20 +230,16 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, return denali->irq_status; } -/* resets a specific device connected to the core */ -static void reset_bank(struct denali_nand_info *denali) +static uint32_t denali_check_irq(struct denali_nand_info *denali) { + unsigned long flags; uint32_t irq_status; - denali_reset_irq(denali); - - iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); - - irq_status = denali_wait_for_irq(denali, - INTR__RST_COMP | INTR__TIME_OUT); + spin_lock_irqsave(&denali->irq_lock, flags); + irq_status = denali->irq_status; + spin_unlock_irqrestore(&denali->irq_lock, flags); - if (!(irq_status & INTR__RST_COMP)) - dev_err(denali->dev, "reset bank failed.\n"); + return irq_status; } /* @@ -273,6 +269,42 @@ static uint8_t denali_read_byte(struct mtd_info *mtd) return ioread32(denali->flash_mem + 0x10); } +static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + index_addr(denali, MODE_11 | BANK(denali->flash_bank) | 2, byte); +} + +static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t type; + + if (ctrl & NAND_CLE) + type = 0; + else if (ctrl & NAND_ALE) + type = 1; + else + return; + + /* + * Some commands are followed by chip->dev_ready or chip->waitfunc. + * irq_status must be cleared here to catch the R/B# interrupt later. + */ + if (ctrl & NAND_CTRL_CHANGE) + denali_reset_irq(denali); + + index_addr(denali, MODE_11 | BANK(denali->flash_bank) | type, dat); +} + +static int denali_dev_ready(struct mtd_info *mtd) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + return !!(denali_check_irq(denali) & INTR__INT_ACT); +} + /* * sends a pipeline command operation to the controller. See the Denali NAND * controller's user guide for more information (section 4.2.3.6). @@ -824,7 +856,13 @@ static void denali_select_chip(struct mtd_info *mtd, int chip) static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) { - return 0; + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t irq_status; + + /* R/B# pin transitioned from low to high? */ + irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); + + return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; } static int denali_erase(struct mtd_info *mtd, int page) @@ -845,46 +883,6 @@ static int denali_erase(struct mtd_info *mtd, int page) return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; } -static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, - int page) -{ - struct denali_nand_info *denali = mtd_to_denali(mtd); - uint32_t addr, irq_status; - int wait_ready = 0; - - switch (cmd) { - case NAND_CMD_PARAM: - wait_ready = 1; - break; - case NAND_CMD_STATUS: - case NAND_CMD_READID: - break; - case NAND_CMD_RESET: - reset_bank(denali); - break; - case NAND_CMD_READOOB: - /* TODO: Read OOB data */ - return; - default: - pr_err(": unsupported command received 0x%x\n", cmd); - return; - } - - denali_reset_irq(denali); - - addr = MODE_11 | BANK(denali->flash_bank); - index_addr(denali, addr | 0, cmd); - if (col != -1) - index_addr(denali, addr | 1, col); - - if (!wait_ready) - return; - - irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); - if (!(irq_status & INTR__INT_ACT)) - dev_err(denali->dev, "failed to issue command 0x%x\n", cmd); -} - #define DIV_ROUND_DOWN_ULL(ll, d) \ ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) @@ -1224,8 +1222,10 @@ int denali_init(struct denali_nand_info *denali) /* register the driver with the NAND core subsystem */ chip->select_chip = denali_select_chip; - chip->cmdfunc = denali_cmdfunc; chip->read_byte = denali_read_byte; + chip->write_byte = denali_write_byte; + chip->cmd_ctrl = denali_cmd_ctrl; + chip->dev_ready = denali_dev_ready; chip->waitfunc = denali_waitfunc; /* clk rate info is needed for setup_data_interface */ if (denali->clk_x_rate)