From patchwork Tue Jun 13 13:45:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 105341 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp414534qgd; Tue, 13 Jun 2017 06:48:42 -0700 (PDT) X-Received: by 10.98.159.88 with SMTP id g85mr30562112pfe.21.1497361721959; Tue, 13 Jun 2017 06:48:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497361721; cv=none; d=google.com; s=arc-20160816; b=fBj5u4AzgGrNosizk2Ox3Y2y3DZZp2gYFxBEFSxMo4yWnztjuAybOSc86/4c81AVjx +Gaqb2zNIuZrabOSM9+qvPgwu5HtddrDOzksRkxICa/89QrMyyxGu/YWPk/Qy/lDIh26 AWON5liMSGkQNXh9n6uXymElIl2wTAR+02FCUlpoEqeLjif/ELl/CugWCjhrBf427ehf mHEaGBjaTvD0tBbzSmv8a2jXQs16hgj9mug+OQkug7qD0fcaKZpw/tbNYh7hPzvLIvCC ryo/vptfebTqv3hEeriSYtn90g32/Yb4U1E/bLW8Xp3t31ceQVbf3027YDxrl2vAz4Vk LixQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=L8eio/VYgqf1QyROSGpGazm4gAz6777JEjyU7drcuJk=; b=VGc0t14kFgcSn6ORIWf1PPpJBB593cQTPvBR+VVP40xeBqPmyjzceTVfQ3aZ1cBAc8 lRQKcHl0UMUTMfxoDE7aGaxo7PRt4SRWaIRCVu2On3wejJFWjlBt+bIrBf4DO1APsZIH 7w+JweiHmSWi8FXdt+8Gy3EJUmq4k63Yv/ofsZ8zfhFU/TFKzznGbw6r6mxGuZyaELfF oUDLqw/M3x1JYCEv9f+joXUbviDyed1BADaD0iIzIc9JGUMB06Xx05N3sbnZ1f5zt8aL axoh9keN7zlvhQnq7+LGHfVQwUujCYry2C0HkPmi8EffmCbsCBZdaHjvuIIoLcNGCqdG Sy9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t20si10163902plj.520.2017.06.13.06.48.41; Tue, 13 Jun 2017 06:48:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753554AbdFMNsg (ORCPT + 25 others); Tue, 13 Jun 2017 09:48:36 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:31022 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753417AbdFMNse (ORCPT ); Tue, 13 Jun 2017 09:48:34 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v5DDjxip031338; Tue, 13 Jun 2017 22:46:10 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v5DDjxip031338 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1497361571; bh=L8eio/VYgqf1QyROSGpGazm4gAz6777JEjyU7drcuJk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QgwhqOwchLflYb7bDRjeW2yMVjiU+V+gWMdOv8bH2QSglpKdKQqqdaviJa14rTOom yoV69Q3FakhbwGS1uMhCbuqIjVyRmXeTnjVqH0n41ax/LKk/See4c8vchgSFMYOPZl EopzgZrRfC5fLOuXYPZVy9EwoHBNIke5izVoZj+HtUwOOOBGXkY+C3fUM0M5Q2uq7V drfoRzmFVqgTzVtN5Hkgrk+v/EVRjXgjPxe0zhkmT5S4K2cgYkTS4mKSVC/ab7MDG0 pUDGvRV72VCUr8iGcMsxr9pNLkuyy5VwhwyjXjxXK5A9IJFDpAScycdHal53NocnPe GHYSB1BJEf+5w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v7 06/16] mtd: nand: denali: fix bank reset function to detect the number of chips Date: Tue, 13 Jun 2017 22:45:40 +0900 Message-Id: <1497361550-8115-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497361550-8115-1-git-send-email-yamada.masahiro@socionext.com> References: <1497361550-8115-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The nand_scan_ident() iterates over maxchips, and calls nand_reset() for each. This driver currently passes the maximum number of banks (=chip selects) supported by the controller as maxchips. So, maxchips is typically 4 or 8. Usually, less number of NAND chips are connected to the controller. This can be a problem for ONFi devices. Now, this driver implements ->setup_data_interface() hook, so nand_setup_data_interface() issues Set Features (0xEF) command, which waits until the chip returns R/B# response. If no chip there, we know it never happens, but the driver still ends up with waiting for a long time. It will finally bail-out with timeout error and the driver will work with existing chips, but unnecessary wait will give a bad user experience. The denali_nand_reset() polls the INTR__RST_COMP and INTR__TIME_OUT bits, but they are always set even if not NAND chip is connected to that bank. To know the chip existence, INTR__INT_ACT bit must be checked; this flag is set only when R/B# is toggled. Since the Reset (0xFF) command toggles the R/B# pin, this can be used to know the actual number of chips, and update denali->max_banks. Signed-off-by: Masahiro Yamada --- Boris mentioned this information can be retrieved from DT (http://patchwork.ozlabs.org/patch/745118/), but I'd like to take time for controller/chip decoupling. I am tackling on that, but not completed yet. I believe this commit stands for denali_pci, at least I do not know how to get the number of chips from PCI. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - Reword commit-log Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 52 +++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 8091ba0916cc..3169ba58c58a 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -85,33 +85,6 @@ static void index_addr(struct denali_nand_info *denali, iowrite32(data, denali->flash_mem + 0x10); } -/* Reset the flash controller */ -static uint16_t denali_nand_reset(struct denali_nand_info *denali) -{ - int i; - - for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR__RST_COMP | INTR__TIME_OUT, - denali->flash_reg + INTR_STATUS(i)); - - for (i = 0; i < denali->max_banks; i++) { - iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); - while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & - (INTR__RST_COMP | INTR__TIME_OUT))) - cpu_relax(); - if (ioread32(denali->flash_reg + INTR_STATUS(i)) & - INTR__TIME_OUT) - dev_dbg(denali->dev, - "NAND Reset operation timed out on bank %d\n", i); - } - - for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR__RST_COMP | INTR__TIME_OUT, - denali->flash_reg + INTR_STATUS(i)); - - return PASS; -} - /* * Use the configuration feature register to determine the maximum number of * banks that the hardware supports. @@ -1053,7 +1026,28 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, return 0; } -/* Initialization code to bring the device up to a known good state */ +static void denali_reset_banks(struct denali_nand_info *denali) +{ + int i; + + denali_clear_irq_all(denali); + + for (i = 0; i < denali->max_banks; i++) { + iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); + while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & + (INTR__RST_COMP | INTR__TIME_OUT))) + cpu_relax(); + if (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & + INTR__INT_ACT)) + break; + } + + dev_dbg(denali->dev, "%d chips connected\n", i); + denali->max_banks = i; + + denali_clear_irq_all(denali); +} + static void denali_hw_init(struct denali_nand_info *denali) { /* @@ -1073,7 +1067,7 @@ static void denali_hw_init(struct denali_nand_info *denali) denali->bbtskipbytes = ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES); detect_max_banks(denali); - denali_nand_reset(denali); + denali_reset_banks(denali); iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->flash_reg + CHIP_ENABLE_DONT_CARE);