From patchwork Mon Jun 19 18:30:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Willy Tarreau X-Patchwork-Id: 105912 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp1014642qgd; Mon, 19 Jun 2017 11:51:08 -0700 (PDT) X-Received: by 10.84.178.131 with SMTP id z3mr31481876plb.175.1497898268762; Mon, 19 Jun 2017 11:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497898268; cv=none; d=google.com; s=arc-20160816; b=q6HvC8J+9PEC5PFs0E4NmLGq6qbr9VHUtCptmhAvQxGBWl2xUmdH7ZEpBJ/Ay+xSAM grqh59vRfAgPY0OmuzkmNhEZbC1EmWAmuN4wN/YXRx+adH3k1rk2tpVJpkFO4ZEoiKfH mmsEo2QuWCFrYvpGPqE7DqNK6pZFHwA1RvJMmdGPO6tz2NDQyO3eKx0Sa/Me41/ymuMk FoZeM8QPlfRnfgM9NI54WAxKD8F13gWinMMINiDKEhrMI5tAsxhj3KSpQV39gUbe7fRZ R27UHtGSplN5XYU0E2MOVDwfb/wN6GOmhLY1OHlIkli/hU8tcE/qyUSdAiBKm99pEGD9 Iqfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=tsR1yFPe6PuJKoGbiyHLlVlwgbp83o2KouhJ2gDfjII=; b=oCY+C0AkWRVAlUVO2Xrx6EV1aFdBRMzffmJugo1Tt49Y8Rwog/axJ4iSxA+fyuOw+Y gNK3Ro5PSZZSqVSFube9XFbkBu2QXi1rS04PcBDqhQw3EjUx6SI0gCZUrP0UP2H181A/ 2GD2HddU+VTnDK5K+CGKC9xV2L1ooLgm5dMkMjlNFAJcczksTHV+yjW/mcEdMmJOgM2R 7Px1nRO/MfTLEPAmhpoMkK2bc4PTcp2eeifrcKFltgq8zUzcSsjqgSB1oubKUocLKR4L n8Hye5JFGwqeKCIO+S7fCrKV6TJ4F3/fPo8g0YtM/H3FU4gNKkR5KB7CRQ6zsI0gRk/6 bGiw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m10si5241864pln.457.2017.06.19.11.51.08; Mon, 19 Jun 2017 11:51:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753436AbdFSSu4 (ORCPT + 25 others); Mon, 19 Jun 2017 14:50:56 -0400 Received: from wtarreau.pck.nerim.net ([62.212.114.60]:52687 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753768AbdFSSiu (ORCPT ); Mon, 19 Jun 2017 14:38:50 -0400 Received: (from willy@localhost) by pcw.home.local (8.15.2/8.15.2/Submit) id v5JIXL0U014970; Mon, 19 Jun 2017 20:33:21 +0200 From: Willy Tarreau To: linux-kernel@vger.kernel.org, stable@vger.kernel.org, linux@roeck-us.net Cc: Mark Rutland , Russell King , Russell King , Willy Tarreau Subject: [PATCH 3.10 104/268] ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs Date: Mon, 19 Jun 2017 20:30:03 +0200 Message-Id: <1497897167-14556-105-git-send-email-w@1wt.eu> X-Mailer: git-send-email 2.8.0.rc2.1.gbe9624a In-Reply-To: <1497897167-14556-1-git-send-email-w@1wt.eu> References: <1497897167-14556-1-git-send-email-w@1wt.eu> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Rutland commit ddc37832a1349f474c4532de381498020ed71d31 upstream. On APQ8060, the kernel crashes in arch_hw_breakpoint_init, taking an undefined instruction trap within write_wb_reg. This is because Scorpion CPUs erroneously appear to set DBGPRSR.SPD when WFI is issued, even if the core is not powered down. When DBGPRSR.SPD is set, breakpoint and watchpoint registers are treated as undefined. It's possible to trigger similar crashes later on from userspace, by requesting the kernel to install a breakpoint or watchpoint, as we can go idle at any point between the reset of the debug registers and their later use. This has always been the case. Given that this has always been broken, no-one has complained until now, and there is no clear workaround, disable hardware breakpoints and watchpoints on Scorpion to avoid these issues. Signed-off-by: Mark Rutland Reported-by: Linus Walleij Reviewed-by: Stephen Boyd Acked-by: Will Deacon Cc: Russell King Signed-off-by: Russell King Signed-off-by: Willy Tarreau --- arch/arm/include/asm/cputype.h | 3 +++ arch/arm/kernel/hw_breakpoint.c | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) -- 2.8.0.rc2.1.gbe9624a diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index dba62cb..f389107 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -58,6 +58,9 @@ #define ARM_CPU_XSCALE_ARCH_V2 0x4000 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 +/* Qualcomm implemented cores */ +#define ARM_CPU_PART_SCORPION 0x510002d0 + extern unsigned int processor_id; #ifdef CONFIG_CPU_CP15 diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 1fd749e..b0b69e9 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1066,6 +1066,22 @@ static int __init arch_hw_breakpoint_init(void) return 0; } + /* + * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD + * whenever a WFI is issued, even if the core is not powered down, in + * violation of the architecture. When DBGPRSR.SPD is set, accesses to + * breakpoint and watchpoint registers are treated as undefined, so + * this results in boot time and runtime failures when these are + * accessed and we unexpectedly take a trap. + * + * It's not clear if/how this can be worked around, so we blacklist + * Scorpion CPUs to avoid these issues. + */ + if ((read_cpuid_id() & 0xff00fff0) == ARM_CPU_PART_SCORPION) { + pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n"); + return 0; + } + has_ossr = core_has_os_save_restore(); /* Determine how many BRPs/WRPs are available. */