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[2607:f8b0:400e:c05::229]) by mx.google.com with ESMTPS id j13si7437393itd.85.2017.07.17.21.22.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jul 2017 21:22:14 -0700 (PDT) Received-SPF: pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c05::229 as permitted sender) client-ip=2607:f8b0:400e:c05::229; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=THr0A1W2; spf=pass (google.com: domain of john.stultz@linaro.org designates 2607:f8b0:400e:c05::229 as permitted sender) smtp.mailfrom=john.stultz@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by mail-pg0-x229.google.com with SMTP id 123so5530308pgj.1 for ; Mon, 17 Jul 2017 21:22:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Lk3M6/qlRHI7qzJlPO8S6F6lcq3iPDyC+4Onyn1xUF8=; b=THr0A1W2mIWH3Szmqm92oNTV0KajXS6A6VaWdytRx2WVaacjzlUxAFR4IGk1ekQaZC YsnqS4CvKWHltQXsIHHma638SQ05CHxMC7cC0Y+qsywi16Bqp9lUE64CvTMp1x8tkq11 lC4G1NHq+1CpJcR6zX/Eu9K0/kBMy4hhKMsUk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Lk3M6/qlRHI7qzJlPO8S6F6lcq3iPDyC+4Onyn1xUF8=; b=qQguG5uDRn1mP8o3dYJJN2G3EEE3D+Ei708pDAS8Jmx1YfVWleJIuDoEZp2J/Wt8dK aHFH/cMa5aAUIKrlavlHLF0XVQ9i+F7j4GLZJWL44MHjYInNENB//A9jPjS2ujEdGKV4 hSE6c4yL7KtzR9T9bRNU/ujbMWNz+qOnuujRWSWg3wCeDAwBj33XaTn79PgnyqC0fQEO zjDCBNs8GQPdeJXZalJ4XwTxmQxITCKCxkfnQzx1lyVno0Glw4PtWza23dCSXS8HtSZN 0M9pSirK/g4syJQFsivj4z+l7FMJlNkUuourDhra737D331ua/FgpjsS1Nvz1hl9aczT zJ2w== X-Gm-Message-State: AIVw113Xn+aPUuDgqDOFlSZXXSv5zzJpLdWbcLXMS1BOj5UNW8QH4wNs qeeLwc6XMFHxTi4FXsg= X-Received: by 10.84.133.38 with SMTP id 35mr1065951plf.141.1500351734071; Mon, 17 Jul 2017 21:22:14 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([2601:1c2:1002:83f0:4e72:b9ff:fe99:466a]) by smtp.gmail.com with ESMTPSA id t4sm1339536pgs.22.2017.07.17.21.22.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Jul 2017 21:22:13 -0700 (PDT) From: John Stultz To: lkml Cc: John Stultz , Daniel Vetter , Jani Nikula , Sean Paul , David Airlie , Rob Clark , Xinliang Liu , Xinliang Liu , Rongrong Zou , Xinwei Kong , Chen Feng , Jose Abreu , Archit Taneja , dri-devel@lists.freedesktop.org Subject: [RFC][PATCH v2] drm: kirin: Add mode_valid logic to avoid mode clocks we can't generate Date: Mon, 17 Jul 2017 21:22:10 -0700 Message-Id: <1500351730-26391-1-git-send-email-john.stultz@linaro.org> X-Mailer: git-send-email 2.7.4 Currently the hikey dsi logic cannot generate accurate byte clocks values for all pixel clock values. Thus if a mode clock is selected that cannot match the calculated byte clock, the device will boot with a blank screen. This patch uses the new mode_valid callback (many thanks to Jose Abreu for upstreaming it!) to ensure we don't select modes we cannot generate. NOTE: Stylistically I suspect there are better ways to do what I'm trying to do here. The encoder -> crtc bit is terrible, and getting the crtc adjusted mode from the encoder logic feels less then ideal. So feedback would be greatly appreciated! Cc: Daniel Vetter Cc: Jani Nikula Cc: Sean Paul Cc: David Airlie Cc: Rob Clark Cc: Xinliang Liu Cc: Xinliang Liu Cc: Rongrong Zou Cc: Xinwei Kong Cc: Chen Feng Cc: Jose Abreu Cc: Archit Taneja Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz --- v2: Reworked to calculate if modeclock matches the phy's byteclock, rather then using a whitelist of known modes. --- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 45 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 8 +++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 2 ++ 3 files changed, 55 insertions(+) -- 2.7.4 diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index f77dcfa..9a553e7 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -24,6 +24,7 @@ #include #include +#include "kirin_drm_drv.h" #include "dw_dsi_reg.h" #define MAX_TX_ESC_CLK 10 @@ -603,6 +604,49 @@ static void dsi_encoder_enable(struct drm_encoder *encoder) dsi->enable = true; } +static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct drm_crtc *crtc = NULL; + struct mipi_phy_params phy; + u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + u32 adjusted_clock; + u32 req_kHz, act_kHz, lane_byte_clk_kHz; + + /* Figure out what the adjusted modeclock will be */ + /* XXX There's got to be a better way to go encoder->crtc */ + drm_for_each_crtc(crtc, encoder->dev) + if (crtc) + break; + if (crtc) + adjusted_clock = kirin_ade_adj_mode_clk(crtc, mode->clock); + else + adjusted_clock = mode->clock; + + /* Calculate the lane byte clk using the adjusted mode clk */ + memset(&phy, 0, sizeof(phy)); + req_kHz = adjusted_clock * bpp / dsi->lanes; + act_kHz = dsi_calc_phy_rate(req_kHz, &phy); + lane_byte_clk_kHz = act_kHz / 8; + + DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i adj_clock: %i...", + mode->hdisplay, mode->vdisplay, bpp, + drm_mode_vrefresh(mode), mode->clock, adjusted_clock); + + /* + * Make sure the adjused mode clock and the lane byte clk + * have a common denominator base frequency + */ + if (adjusted_clock/dsi->lanes == lane_byte_clk_kHz/3) { + DRM_DEBUG_DRIVER("OK!\n"); + return MODE_OK; + } + + DRM_DEBUG_DRIVER("BAD!\n"); + return MODE_BAD; +} + static void dsi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -622,6 +666,7 @@ static int dsi_encoder_atomic_check(struct drm_encoder *encoder, static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { .atomic_check = dsi_encoder_atomic_check, + .mode_valid = dsi_encoder_mode_valid, .mode_set = dsi_encoder_mode_set, .enable = dsi_encoder_enable, .disable = dsi_encoder_disable diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 074b0af..dffcf76 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -178,6 +178,14 @@ static void ade_init(struct ade_hw_ctx *ctx) FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); } +u32 kirin_ade_adj_mode_clk(struct drm_crtc *crtc, u32 modeclk) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + return clk_round_rate(ctx->ade_pix_clk, modeclk * 1000) / 1000; +} + static void ade_set_pix_clk(struct ade_hw_ctx *ctx, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h index 7f60c649..85f69ee 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h @@ -27,4 +27,6 @@ struct kirin_drm_private { extern const struct kirin_dc_ops ade_dc_ops; +u32 kirin_ade_adj_mode_clk(struct drm_crtc *crtc, u32 modeclk); + #endif /* __KIRIN_DRM_DRV_H__ */