From patchwork Tue Jul 18 16:59:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 108154 Delivered-To: patch@linaro.org Received: by 10.182.45.195 with SMTP id p3csp6150813obm; Tue, 18 Jul 2017 10:01:56 -0700 (PDT) X-Received: by 10.84.174.131 with SMTP id r3mr2821278plb.37.1500397316334; Tue, 18 Jul 2017 10:01:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500397316; cv=none; d=google.com; s=arc-20160816; b=Xq6eKnkIncjvyJD/x9j0j3f5bM+AZ0de7s67G8nUkTaRCk1LA1jM6aq2X+C8pPO2aC 2bnDTZbehpSVaz6Q9yjikB5Xi6ZiTcEPq8I4gwzPuNbfgwu9Fm8SuaMDSMr9WPEVzGin +QWEHw5rwHNKUr29Kav2scdNYyM5qpzIORFGZJ2rEVhkdumw6uL6C6bWuiyLdTsJSMFn Zgh8JigtoHK7+sYGae7uAMhISn+vpv5jZlT3KYIILlvRjbMbbxe/P6XAZiaQxmcgHsTY lC2O7AulEAERUCEefjFvq+5NPZbNK1C2gWdl7uipNeznOdY0HA0oZpgRASvxLGvbAlJ7 ZCOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OOF9AZOhyQnGj90EyLshg2YsG0V5UbJ0K1562QZ9LEs=; b=AOLknVnrb9AHi7+J9fUTdO2Llj4Wpbro9M141XEisn9N1pWGBdYuFS/rK2h4po0sZy G8GRO00kFSEghdWJnFpQMrOjDJPbr3JvxsIxkq6qoqkD2wOuJEAjIBJLLvqTNuL/q+Pg b1f6Oe51Df41FsSy/e0gjBqeWvA0G97Ni17tbbAhxmynFUWg78ZVlS4eiVYsdbee1l/+ 3ROPceGpIj5I40Pvvs47h4PiPDKFlfuKzgT/wLuxmyYH6qNJa22lsdO0ylLBYOxNpEzH GTFwL38VmU3dPSrTBu85+ILgiVjXJzCudGnpz/cW4HkwKleR0mH+Be4ZPAwpWGzzA1QE RtsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=eH2zfYvK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y186si2130694pfg.260.2017.07.18.10.01.55; Tue, 18 Jul 2017 10:01:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=eH2zfYvK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752165AbdGRRBw (ORCPT + 25 others); Tue, 18 Jul 2017 13:01:52 -0400 Received: from mail-it0-f54.google.com ([209.85.214.54]:37842 "EHLO mail-it0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752506AbdGRRAi (ORCPT ); Tue, 18 Jul 2017 13:00:38 -0400 Received: by mail-it0-f54.google.com with SMTP id v127so6953227itd.0 for ; Tue, 18 Jul 2017 10:00:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OOF9AZOhyQnGj90EyLshg2YsG0V5UbJ0K1562QZ9LEs=; b=eH2zfYvKoyegcUA0xitJ8hcHeMVLShtELvkV1GCdviPlZ/MSIlTEbFhI0Cu9tajCAE IKX/lpBD/xS1i67DcfvXXwVgHTfn+/oJEJS1sBjSOYEPn0vIj/HLzx5zZzG5Z1GE5ng6 /RnB9vwTXFVKLMqoE9iQfnzniRAVs9qqEtvIc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OOF9AZOhyQnGj90EyLshg2YsG0V5UbJ0K1562QZ9LEs=; b=XXFUAVdrd/0u7LPYfzxXxbrFZ1ubQILZcKR/S6hKLiIw6o9oofALPANnuGPR8M4GWO Bj7H/5KnwDT49uLyCoJNlVCmyH+XVChUP1CfIpsowrYkfHf9KrHoTMggCeZS29ppzRhI BokmMI/oj+qWZUmBksI1HTbZ5qJBPnGSOjTfB4HUSvyDesTNmDKTlAm5R5XqZZPqRMRP mHmWAazJysJBUx49XQub0V/OaCn9h4F6gcKv/yMMsPpannp0sxGuTyA1Ycr2BUezWUYE ZVWW2GBz4XkFnrz2nlJ7q++EUWQWUTz8sD6UoFd3R22+Cnnd2GqMWKkcL3Yzu4pZvwdr VdFA== X-Gm-Message-State: AIVw1122yL6vfGKhFcoJkeI2XD2ledOaSkZNRCr4t7nMesSYZAa7wk4K V9j/TD+NQRZoBs0M X-Received: by 10.36.55.22 with SMTP id r22mr3732336itr.71.1500397237469; Tue, 18 Jul 2017 10:00:37 -0700 (PDT) Received: from node.jintackl-qv26972.kvmarm-pg0.wisc.cloudlab.us (c220g1-030822.wisc.cloudlab.us. [128.104.222.82]) by smtp.gmail.com with ESMTPSA id j96sm1413075ioo.49.2017.07.18.10.00.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Jul 2017 10:00:36 -0700 (PDT) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: corbet@lwn.net, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, mchehab@kernel.org, cov@codeaurora.org, daniel.lezcano@linaro.org, david.daney@cavium.com, mark.rutland@arm.com, suzuki.poulose@arm.com, stefan@hello-penguin.com, andy.gross@linaro.org, wcohen@redhat.com, ard.biesheuvel@linaro.org, shankerd@codeaurora.org, vladimir.murzin@arm.com, james.morse@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jintack Lim Subject: [RFC PATCH v2 35/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting for EL12 register traps Date: Tue, 18 Jul 2017 11:59:01 -0500 Message-Id: <1500397144-16232-36-git-send-email-jintack.lim@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> References: <1500397144-16232-1-git-send-email-jintack.lim@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In addition to EL2 register accesses, setting NV bit will also make EL12 register accesses trap to EL2. To emulate this for the virtual EL2, forword traps due to EL12 register accessses to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 1.9.1 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4fd7090..3559cf7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -149,6 +149,9 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, int i; const struct el1_el2_map *map; + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * Redirect EL1 register accesses to the corresponding EL2 registers if * they are meant to access EL2 registers. @@ -959,6 +962,9 @@ static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); return true; } @@ -1005,6 +1011,9 @@ static bool access_elr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.elr_el1); return true; } @@ -1013,6 +1022,9 @@ static bool access_spsr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu->arch.ctxt.gp_regs.spsr[KVM_SPSR_EL1]); return true; } @@ -1021,6 +1033,9 @@ static bool access_vbar(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + access_rw(p, &vcpu_sys_reg(vcpu, r->reg)); return true; } @@ -1031,6 +1046,9 @@ static bool access_cpacr(struct kvm_vcpu *vcpu, { u64 reg = sys_reg(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); + if (el12_reg(p) && forward_nv_traps(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_hsr(vcpu)); + /* * When the virtual HCR_EL2.E2H == 1, an access to CPACR_EL1 * in the virtual EL2 is to access CPTR_EL2.