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[209.132.180.67]) by mx.google.com with ESMTP id j61si654167plb.534.2017.08.29.02.35.58; Tue, 29 Aug 2017 02:35:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OGPeB1A6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752107AbdH2Jfz (ORCPT + 26 others); Tue, 29 Aug 2017 05:35:55 -0400 Received: from mail-wm0-f54.google.com ([74.125.82.54]:36427 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdH2Jfv (ORCPT ); Tue, 29 Aug 2017 05:35:51 -0400 Received: by mail-wm0-f54.google.com with SMTP id b82so16996304wmd.1 for ; Tue, 29 Aug 2017 02:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rBku61CsbHrdE21oKXSrwh6LJpkkFzAAvkadjAT5GKQ=; b=OGPeB1A6s8BN/A6gPqvA7tTrHErD83rlDOXSaaOc8hVLG4vj29o1q/FVlRvOymHPJn bX/cI2qNmd+urmbikOpDeXXL8D2v7JLkBiqwgs7d4ftxuj3FEN3Bo6Zp/0IaczyB5OlA QNseb8meiSU0VKePr8LEzSPR5ddGbp+H5uW9E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rBku61CsbHrdE21oKXSrwh6LJpkkFzAAvkadjAT5GKQ=; b=NxS9EsxoovUx/x1MxZfsZZfUJaDmBa6tVit097idsz+PgTjbAKM1yTrS2HsYOsSnBH sFEBa0KKmuW1nCWF8Dl1IdjVcDvZVDFDkwUYHFpmzD89JkliDLXs/1ah+iPuPqTXFuss H8OYol45TlqBVk24LHr8PlpCE138ECtQXjoTE9gxDEkuI9XDy1Xi/Qkws5j1n1YL7Qs/ /dMqPM8sPuxbZlr6czMhvaG5rcNl3j6voRbEb0iBILvnz94Ik0WDX0JazSsNUwh2bPhx /Om1Ivjg5QEcXdtAmBIVYUyRlIQHIfmHEHWW9i2bUs2YlnMIIydOlirBfEVtyZI0CsLw Zipw== X-Gm-Message-State: AHYfb5jSmiJqiNXeoqhR8zFjjITfehWl39AYVlbd/9iUyRuCw9OFJ8pY aZddUL4xJRE1fMO+ X-Received: by 10.28.149.137 with SMTP id x131mr827184wmd.53.1503999350055; Tue, 29 Aug 2017 02:35:50 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:49 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dong Aisheng , Arnd Bergmann , Shawn Guo , Anson Huang , Bai Ping Subject: [PATCH 2/9] clocksource/drivers/imx-tpm: Add imx tpm timer support Date: Tue, 29 Aug 2017 11:34:20 +0200 Message-Id: <1503999271-15712-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dong Aisheng IMX Timer/PWM Module (TPM) supports both timer and pwm function while this patch only adds the timer support. PWM would be added later. The TPM counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes. NOTE: We observed in a very small probability, the bus fabric contention between GPU and A7 may results a few cycles delay of writing CNT registers which may cause the min_delta event got missed, so we need add a ETIME check here in case it happened. Cc: Daniel Lezcano Cc: Arnd Bergmann Cc: Thomas Gleixner Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 drivers/clocksource/timer-imx-tpm.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index fcae5ca..0a953fc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -598,6 +598,14 @@ config CLKSRC_IMX_GPT depends on ARM && CLKDEV_LOOKUP select CLKSRC_MMIO +config CLKSRC_IMX_TPM + bool "Clocksource using i.MX TPM" if COMPILE_TEST + depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + help + Enable this option to use IMX Timer/PWM Module (TPM) timer as + clocksource. + config CLKSRC_ST_LPC bool "Low power clocksource found in the LPC" if COMPILE_TEST select TIMER_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 6df9494..dbc1ad1 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o +obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c new file mode 100644 index 0000000..21bffdc --- /dev/null +++ b/drivers/clocksource/timer-imx-tpm.c @@ -0,0 +1,239 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPM_SC 0x10 +#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) +#define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_CNT 0x14 +#define TPM_MOD 0x18 +#define TPM_STATUS 0x1c +#define TPM_STATUS_CH0F BIT(0) +#define TPM_C0SC 0x20 +#define TPM_C0SC_CHIE BIT(6) +#define TPM_C0SC_MODE_SHIFT 2 +#define TPM_C0SC_MODE_MASK 0x3c +#define TPM_C0SC_MODE_SW_COMPARE 0x4 +#define TPM_C0V 0x24 + +static void __iomem *timer_base; +static struct clock_event_device clockevent_tpm; + +static inline void tpm_timer_disable(void) +{ + unsigned int val; + + /* channel disable */ + val = readl(timer_base + TPM_C0SC); + val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE); + writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_timer_enable(void) +{ + unsigned int val; + + /* channel enabled in sw compare mode */ + val = readl(timer_base + TPM_C0SC); + val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) | + TPM_C0SC_CHIE; + writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_irq_acknowledge(void) +{ + writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS); +} + +static struct delay_timer tpm_delay_timer; + +static inline unsigned long tpm_read_counter(void) +{ + return readl(timer_base + TPM_CNT); +} + +static unsigned long tpm_read_current_timer(void) +{ + return tpm_read_counter(); +} + +static u64 notrace tpm_read_sched_clock(void) +{ + return tpm_read_counter(); +} + +static int __init tpm_clocksource_init(unsigned long rate) +{ + tpm_delay_timer.read_current_timer = &tpm_read_current_timer; + tpm_delay_timer.freq = rate; + register_current_timer_delay(&tpm_delay_timer); + + sched_clock_register(tpm_read_sched_clock, 32, rate); + + return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", + rate, 200, 32, clocksource_mmio_readl_up); +} + +static int tpm_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned long next, now; + + next = tpm_read_counter(); + next += delta; + writel(next, timer_base + TPM_C0V); + now = tpm_read_counter(); + + /* + * NOTE: We observed in a very small probability, the bus fabric + * contention between GPU and A7 may results a few cycles delay + * of writing CNT registers which may cause the min_delta event got + * missed, so we need add a ETIME check here in case it happened. + */ + return (int)((next - now) <= 0) ? -ETIME : 0; +} + +static int tpm_set_state_oneshot(struct clock_event_device *evt) +{ + tpm_timer_enable(); + + return 0; +} + +static int tpm_set_state_shutdown(struct clock_event_device *evt) +{ + tpm_timer_disable(); + + return 0; +} + +static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + tpm_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct clock_event_device clockevent_tpm = { + .name = "i.MX7ULP TPM Timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_oneshot = tpm_set_state_oneshot, + .set_next_event = tpm_set_next_event, + .set_state_shutdown = tpm_set_state_shutdown, + .rating = 200, +}; + +static int __init tpm_clockevent_init(unsigned long rate, int irq) +{ + int ret; + + ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, + "i.MX7ULP TPM Timer", &clockevent_tpm); + + clockevent_tpm.cpumask = cpumask_of(0); + clockevent_tpm.irq = irq; + clockevents_config_and_register(&clockevent_tpm, + rate, 300, 0xfffffffe); + + return ret; +} + +static int __init tpm_timer_init(struct device_node *np) +{ + struct clk *ipg, *per; + int irq, ret; + u32 rate; + + timer_base = of_iomap(np, 0); + if (!timer_base) { + pr_err("tpm: failed to get base address\n"); + return -ENXIO; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("tpm: failed to get irq\n"); + ret = -ENOENT; + goto err_iomap; + } + + ipg = of_clk_get_by_name(np, "ipg"); + per = of_clk_get_by_name(np, "per"); + if (IS_ERR(ipg) || IS_ERR(per)) { + pr_err("tpm: failed to get igp or per clk\n"); + ret = -ENODEV; + goto err_clk_get; + } + + /* enable clk before accessing registers */ + ret = clk_prepare_enable(ipg); + if (ret) { + pr_err("tpm: ipg clock enable failed (%d)\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(per); + if (ret) { + pr_err("tpm: per clock enable failed (%d)\n", ret); + goto err_per_clk_enable; + } + + /* + * Initialize tpm module to a known state + * 1) Counter disabled + * 2) TPM counter operates in up counting mode + * 3) Timer Overflow Interrupt disabled + * 4) Channel0 disabled + * 5) DMA transfers disabled + */ + writel(0, timer_base + TPM_SC); + writel(0, timer_base + TPM_CNT); + writel(0, timer_base + TPM_C0SC); + + /* increase per cnt, div 8 by default */ + writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, + timer_base + TPM_SC); + + /* set MOD register to maximum for free running mode */ + writel(0xffffffff, timer_base + TPM_MOD); + + rate = clk_get_rate(per) >> 3; + ret = tpm_clocksource_init(rate); + if (ret) + goto err_per_clk_enable; + + ret = tpm_clockevent_init(rate, irq); + if (ret) + goto err_per_clk_enable; + + return 0; + +err_per_clk_enable: + clk_disable_unprepare(ipg); +err_clk_get: + clk_put(per); + clk_put(ipg); +err_iomap: + iounmap(timer_base); + return ret; +} +TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);