From patchwork Thu Sep 28 14:09:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 114449 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp791167qgf; Thu, 28 Sep 2017 07:11:11 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCE3lUxwsbokoUBeKIpiYGaMsTtzHUsyDh0nLtPV/sDi5/7QWHogoELbiXitQkxvKxncDw4 X-Received: by 10.84.218.141 with SMTP id r13mr4024619pli.271.1506607870966; Thu, 28 Sep 2017 07:11:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506607870; cv=none; d=google.com; s=arc-20160816; b=m1GL7hGmhfGrEZxDroZDrNA+QRMpKdHHyZvP3qCdufZFzZiUpPwvH/Qs8+8PmkECWR XFyg4F8vh3tkK/gvLoYudDzda2vGhm75rBmAqo0mV/FiKPMRA8+EGE2XckAm8c7jsHkI 3rXmF/tBh5BD+1jM8NzN6l31jhfuPZaTBOcIBMtezFjcA3Kcre4bZtFU3WwfWPQHwsYj HZiJmTeEATTl2iwIsHT4cSI5Sam8qtBYwULnIiFyVdMwwCj6RBp7JMpb0rne89Ap4/J8 9e7GHES5Xv93W0woZl1mEjWxS8mdUKpPN6YgUdfrLvGJcEGI8jDGvZSE+Yw76Q+sP8oB IhuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=YJekJiEJQ9B4O3k+UB43UEbf/bJeVTEd9xHNMwHWv8Q=; b=OQFLDhJV9hViZqm7roaOZwGMimH6aFOefBq5UDv0/uxugFGqVDvqUuT9WQJ5jBiQlt +kVZvFvZ5qO0Zzyr7wcOgJGk2h6qjgI8Nx/IJ13ncaAotib+4JGrr7yVtMPzBTY/Rl1G 3fk0KHaHoYGV/3QGZzf2Qlifa7EojBbaKJSb8LyHWGHoy1lynOTb+a5nPTY+I/RQU9Vh 869iWEhQ3NhPQSbChg/Syh4f5NnULejCnb/LZZTYjipEgHdgr23fbGgCwz4dxeuyFLCU DpLu8XbBPuEcW815s0YuQBVHWhLqyeZYERKYyMoGy/+uImQDqyzPE0vZcAoW26Z6cpqY fjxw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e62si1477418pfa.483.2017.09.28.07.11.10; Thu, 28 Sep 2017 07:11:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932113AbdI1OLI (ORCPT + 26 others); Thu, 28 Sep 2017 10:11:08 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:58242 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751346AbdI1OJj (ORCPT ); Thu, 28 Sep 2017 10:09:39 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2EC41682; Thu, 28 Sep 2017 07:09:38 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C4A1E3F483; Thu, 28 Sep 2017 07:09:38 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id B74FF1AE3085; Thu, 28 Sep 2017 15:09:52 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com, mark.rutland@arm.com, kim.phillips@arm.com, tglx@linutronix.de, peterz@infradead.org, alexander.shishkin@linux.intel.com, robh@kernel.org, suzuki.poulose@arm.com, pawel.moll@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, linux-kernel@vger.kernel.org, Will Deacon Subject: [PATCH v5 5/7] arm64: head: Init PMSCR_EL2.{PA, PCT} when entered at EL2 without VHE Date: Thu, 28 Sep 2017 15:09:49 +0100 Message-Id: <1506607791-8621-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1506607791-8621-1-git-send-email-will.deacon@arm.com> References: <1506607791-8621-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When booting at EL2, ensure that we permit the EL1 host to sample physical addresses and physical counter values using SPE. Signed-off-by: Will Deacon --- arch/arm64/kernel/head.S | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.1.4 Acked-by: Mark Rutland diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 7434ec0c7a27..c370e270ae55 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -479,14 +479,21 @@ set_hcr: /* Statistical profiling */ ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer - cbz x0, 6f // Skip if SPE not present - cbnz x2, 5f // VHE? + cbz x0, 7f // Skip if SPE not present + cbnz x2, 6f // VHE? + mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, + and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + cbnz x4, 5f // then permit sampling of physical + mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ + 1 << SYS_PMSCR_EL2_PA_SHIFT) + msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter +5: mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) orr x3, x3, x1 // If we don't have VHE, then - b 6f // use EL1&0 translation. -5: // For VHE, use EL2 translation + b 7f // use EL1&0 translation. +6: // For VHE, use EL2 translation orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 -6: +7: msr mdcr_el2, x3 // Configure debug traps /* Stage-2 translation */