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[209.132.180.67]) by mx.google.com with ESMTP id e23si4176393pfd.376.2017.10.02.08.52.59; Mon, 02 Oct 2017 08:52:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QcBGpO18; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752025AbdJBPw5 (ORCPT + 26 others); Mon, 2 Oct 2017 11:52:57 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:49994 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751916AbdJBPwP (ORCPT ); Mon, 2 Oct 2017 11:52:15 -0400 Received: by mail-wr0-f169.google.com with SMTP id p10so2513978wrc.6 for ; Mon, 02 Oct 2017 08:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YRMDrn0GKD9HNuTlCPy7fMgZ2opjSCTXVxBYgWeWkDc=; b=QcBGpO18uLTrmGNxyu5R8iW7q8EQhN32jlGYOlsHTUWMHKGJAYXyMfb4RbKj6gexcn uZFnIBtREkKUOMFRouie+Q8DlydoD6aUBACIFeh+Uatjs61XlcYz5QLWM6w3MrnsudIw N2evfEXqh8jIB272B1l3Q7hExMLYQ98W1APB0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YRMDrn0GKD9HNuTlCPy7fMgZ2opjSCTXVxBYgWeWkDc=; b=r1em8vQV/S4vB5r6Xkw77znvQ0f6wF7YgFfWD1uAUIpRScuaT7wuvxjBi4a11c9pyD MtbcjRQPrCpJ6pZyeQ71c7LFKbMNqjS96UXPZC1ff+yCep9O09ebWnilKnpdrz5CUhca If4bogZ8uS1z5vI+2XInyDaJwbHMVvN/1TL2BdXjuY5GuNG4QjMfjMttTCrRIi0SeHsB RdD7mh47pXJMLt3b4xzQTNlVI3/HwEFR7prV8jIszgmzCgDwXwbYv3AVEpuFDHPQM27D yitd9wJEevqbp4xWZKTmpL8P4atG9n2ew0sNg3mNhIaFzMCQLpgH8+am0EKfS0Z2eg4l NTRw== X-Gm-Message-State: AHPjjUjvaDK1tVPAHDYqWje7/72+InPiXTioUGZ7nX/vFTTTYB4mauf9 GfjmYvefPJpXZgqSMtV1MGYUQxwJbFk= X-Google-Smtp-Source: AOwi7QCtMuIvO4Og+A0zgrAj3kpg0SRD/odDDGZZDyOXt1WkRvGprW7norKltzF9v33GyX8oueZ2GQ== X-Received: by 10.223.132.101 with SMTP id 92mr14625474wrf.85.1506959534338; Mon, 02 Oct 2017 08:52:14 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.74.152]) by smtp.gmail.com with ESMTPSA id w5sm6724879wrg.65.2017.10.02.08.52.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Oct 2017 08:52:13 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v4 2/4] clocksource: stm32: only use 32 bits timers Date: Mon, 2 Oct 2017 17:51:51 +0200 Message-Id: <1506959513-16851-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506959513-16851-1-git-send-email-benjamin.gaignard@linaro.org> References: <1506959513-16851-1-git-send-email-benjamin.gaignard@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 16 bits hardware are not enough accure to be used. Do no allow them to be probed by tested max counter value. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index abff21c..f7e4eec 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -81,9 +81,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -113,26 +113,21 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + return -EINVAL; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), 0x60, ~0U); return 0; }