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[209.132.180.67]) by mx.google.com with ESMTP id p91si671185plb.301.2017.10.17.20.18.04; Tue, 17 Oct 2017 20:18:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933933AbdJRDSD (ORCPT + 27 others); Tue, 17 Oct 2017 23:18:03 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:8524 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933691AbdJRDR5 (ORCPT ); Tue, 17 Oct 2017 23:17:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS408-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJI64663; Wed, 18 Oct 2017 11:17:55 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 11:17:44 +0800 From: Jiancheng Xue To: , CC: , , , , , , , tianshuliang Subject: [PATCH 3/3] arm64: dts: hisilicon: supplement properties of emmc nodes for hi3798cv200-poplar board Date: Wed, 18 Oct 2017 07:22:08 -0400 Message-ID: <1508325728-55823-4-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508325728-55823-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508325728-55823-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.59E6C7E3.0075, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b63bc3a776a368a15e8f3a2c7e454039 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: tianshuliang Supplement properties of emmc nodes to support high performance. Signed-off-by: tianshuliang --- arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | 12 ++++++++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 +++++--- 2 files changed, 17 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 6a0b7e9..b890829 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -160,4 +160,16 @@ status = "okay"; label = "LS-UART0"; }; + +&emmc { + status = "okay"; + num-slots = <1>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; +}; /* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 5a73c68..df62382 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -241,12 +241,14 @@ }; emmc: mmc@9830000 { - compatible = "snps,dw-mshc"; + compatible = "hisilicon,hi3798cv200-dw-mshc"; reg = <0x9830000 0x10000>; interrupts = ; clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; }; gpio0: gpio@8b20000 {