From patchwork Fri Nov 17 18:21:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 119202 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp845441qgn; Fri, 17 Nov 2017 10:24:40 -0800 (PST) X-Google-Smtp-Source: AGs4zMb/sRw3wuHvcpQPJc0jzxlnOSv6TW7nIAYaoXTbNm207TwYatenNpiuSV7pMZ0MrQCaRf/2 X-Received: by 10.99.152.68 with SMTP id l4mr6006134pgo.208.1510943080336; Fri, 17 Nov 2017 10:24:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510943080; cv=none; d=google.com; s=arc-20160816; b=wVPyuQcExvinzK8+s8LKsBkOdv2/VSXCXmoyiCF76WyenBHrEWTO/j1Qmx14WZBakt uFrcMLNg/Fo1xo0gpKMFUBIrHUVyoMiQT0Xqi1pCXLB56gy1+/oRIS0ObxfY/uXywhM8 pijtkzwNYpRYzc6o/XJnV86ZliGJux5ibpdLs796NF5AQ+Gf9B4+fR1xEhUn6ts7BaVG mP5vGe/W9ejvT/GdQTnug2F8MOI+O3Na/M4TugLViZwAsEkMfu+6c5os6NzAHB2ULPzD 5wEPcNHayJlgusWbe+SK5Wf3CIH7ZXcB8J+9E1u+S9s5z+Ly91jp6R8gvOnQTCLJKGLG swPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=rUJlN0Kz1Z+NoaEhUmAaI1XRcGMCMkwe2PvIgD5P3xw=; b=DMUdhyFevf19zic5euWqRm1cc7/oOd5hP1VIgujHaEDuagfNuYFCHeDrKdWdwXUVm3 A7fAvcpGQPsRQszKsUa0ewWRV/X5R2xsuaeKXyq4MlSb+cEgw9YIMVBR902sqh8d1tyl m52lKRVBSI0POwFn2qL706nQ2SRlvj6KI1ZzVo2NBgBbLT2fRdUpy0Snr5ae56wDXP0I MSsvcbJgFH1Kcsh5AHuEYDgWTJ+hHa83tX5sGJEv7f6iBlwxhMVsRwR41SWyNXeIrhAI WOEIjA0G+WxDiJ6fZb9oOIqq1kdKTAaItB9Pc4t/rLtkoEd5hNxYd6NKHY79PoS3oz22 f0jQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p8si2041682plo.63.2017.11.17.10.24.39; Fri, 17 Nov 2017 10:24:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760412AbdKQSYf (ORCPT + 28 others); Fri, 17 Nov 2017 13:24:35 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39474 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760303AbdKQSV7 (ORCPT ); Fri, 17 Nov 2017 13:21:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32DFF1993; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 041EC3F599; Fri, 17 Nov 2017 10:21:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9DF581AE1384; Fri, 17 Nov 2017 18:22:03 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, Will Deacon Subject: [PATCH 12/18] arm64: entry: Explicitly pass exception level to kernel_ventry macro Date: Fri, 17 Nov 2017 18:21:55 +0000 Message-Id: <1510942921-12564-13-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1510942921-12564-1-git-send-email-will.deacon@arm.com> References: <1510942921-12564-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We will need to treat exceptions from EL0 differently in kernel_ventry, so rework the macro to take the exception level as an argument and construct the branch target using that. Signed-off-by: Will Deacon --- arch/arm64/kernel/entry.S | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index d850af724c8c..e98cf3064509 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -70,7 +70,7 @@ #define BAD_FIQ 2 #define BAD_ERROR 3 - .macro kernel_ventry label + .macro kernel_ventry, el, label, regsize = 64 .align 7 sub sp, sp, #S_FRAME_SIZE #ifdef CONFIG_VMAP_STACK @@ -83,7 +83,7 @@ tbnz x0, #THREAD_SHIFT, 0f sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp - b \label + b el\()\el\()_\label 0: /* @@ -115,7 +115,7 @@ sub sp, sp, x0 mrs x0, tpidrro_el0 #endif - b \label + b el\()\el\()_\label .endm .macro kernel_entry, el, regsize = 64 @@ -366,31 +366,31 @@ tsk .req x28 // current thread_info .align 11 ENTRY(vectors) - kernel_ventry el1_sync_invalid // Synchronous EL1t - kernel_ventry el1_irq_invalid // IRQ EL1t - kernel_ventry el1_fiq_invalid // FIQ EL1t - kernel_ventry el1_error_invalid // Error EL1t + kernel_ventry 1, sync_invalid // Synchronous EL1t + kernel_ventry 1, irq_invalid // IRQ EL1t + kernel_ventry 1, fiq_invalid // FIQ EL1t + kernel_ventry 1, error_invalid // Error EL1t - kernel_ventry el1_sync // Synchronous EL1h - kernel_ventry el1_irq // IRQ EL1h - kernel_ventry el1_fiq_invalid // FIQ EL1h - kernel_ventry el1_error_invalid // Error EL1h + kernel_ventry 1, sync // Synchronous EL1h + kernel_ventry 1, irq // IRQ EL1h + kernel_ventry 1, fiq_invalid // FIQ EL1h + kernel_ventry 1, error_invalid // Error EL1h - kernel_ventry el0_sync // Synchronous 64-bit EL0 - kernel_ventry el0_irq // IRQ 64-bit EL0 - kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0 - kernel_ventry el0_error_invalid // Error 64-bit EL0 + kernel_ventry 0, sync // Synchronous 64-bit EL0 + kernel_ventry 0, irq // IRQ 64-bit EL0 + kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 + kernel_ventry 0, error_invalid // Error 64-bit EL0 #ifdef CONFIG_COMPAT - kernel_ventry el0_sync_compat // Synchronous 32-bit EL0 - kernel_ventry el0_irq_compat // IRQ 32-bit EL0 - kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 - kernel_ventry el0_error_invalid_compat // Error 32-bit EL0 + kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 + kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 + kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 + kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 #else - kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0 - kernel_ventry el0_irq_invalid // IRQ 32-bit EL0 - kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0 - kernel_ventry el0_error_invalid // Error 32-bit EL0 + kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 + kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 + kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 + kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 #endif END(vectors)